chipsalliance/chisel

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Chisel: A Modern Hardware Design Language

Stars: 4.8k
Forks: 658
Open beginner issues: 0
Indexed issues: 354
Avg merge: 18h 59m
Merged PRs (30d): 14

Dominant language: Scala
License: Apache-2.0
Last GitHub push: Sep 10, 2026
Latest indexed: Sep 15, 2026
Contributing guide: Contributing guide
Code of conduct: Code of conduct
Beginner labels: good first issue help wanted

Open All

354 open issues indexed

Type after shift in IntelliJ Open

chipsalliance/chisel#1125 · 6 comments · 1 reaction · 0 assignees · Indexed Sep 15, 2026
Posedge and negedge signal Open

chipsalliance/chisel#1131 · 5 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Counter-intuitive user experience (UX) for simple constant addition Open

usability

chipsalliance/chisel#1144 · 8 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Remove implicit width truncation / Don't repeat Verilog's assignment issue in Chisel Open

strict-semantics

chipsalliance/chisel#1163 · 49 comments · 18 reactions · 0 assignees · Indexed Sep 15, 2026
Incorrect Error Message in Data.connect(...) Open

good first issue

chipsalliance/chisel#1170 · 9 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
TopWiring API Open

chipsalliance/chisel#1178 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Absorb rocket.DecodeLogic into Standard Library Open

chipsalliance/chisel#1187 · 12 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Get width of value using the size of string for UInt, SInt, ... Open

chipsalliance/chisel#1189 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 15, 2026
[rfc] Case/If Else Statement Emission Open

chipsalliance/chisel#1198 · 6 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Esoteric Reverse Open

chipsalliance/chisel#1200 · 0 comments · 1 reaction · 0 assignees · Indexed Sep 15, 2026
Add stacked source locators Open

chipsalliance/chisel#1219 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Better error message for Vec mono-connected to Seq Open

chipsalliance/chisel#1220 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
chisel3.Driver.execute seems to emit anno file after FIRRTL invocation now Open

chipsalliance/chisel#1221 · 0 comments · 0 reactions · 1 assignee · Indexed Sep 15, 2026
Fill 0 returns type instead of value Open

bug

chipsalliance/chisel#1230 · 2 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Bad error message for switch(){is()} if multiple is() with same value. Open

chipsalliance/chisel#1233 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Make literal handling consistent and reliable for FixedPoint and Interval and others Open

bug Feature

chipsalliance/chisel#1272 · 0 comments · 0 reactions · 1 assignee · Indexed Sep 15, 2026
Update logging to have name of design in "Elaborating design..." Open

chipsalliance/chisel#1287 · 8 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Memory with write masks result in confusing layout and readmemh() behaviour Open

bug

chipsalliance/chisel#1289 · 2 comments · 1 reaction · 0 assignees · Indexed Sep 15, 2026
loadMemoryFromFile() should place readmemh() inline for better compatibility Open

chipsalliance/chisel#1293 · 18 comments · 2 reactions · 1 assignee · Indexed Sep 15, 2026
asUInt for bundle literals may be inconsistent Open

chipsalliance/chisel#1297 · 2 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Lazy val ports material ports in parent of modules where the lazy val is defined Open

chipsalliance/chisel#1328 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Naming of ready/valid interface Open

API Modification feature request

chipsalliance/chisel#1350 · 8 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Current Implementation of Counter makes it impossible to create a 32bit or larger counter Open

Feature

chipsalliance/chisel#1362 · 6 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Manipulating Bundles in tests Open

chipsalliance/chisel#1364 · 2 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Maybe adding chisel3.Driver.apply() Open

chipsalliance/chisel#1368 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Support `$` in port names Open

bug

chipsalliance/chisel#1391 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Chisel and Treadle need an elegant Plusargs mechanism Open

feature request

chipsalliance/chisel#1396 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
How about providing `pwhen` or parallelWhen Open

chipsalliance/chisel#1401 · 5 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Allow subword assignment Open

feature request

chipsalliance/chisel#1423 · 4 comments · 2 reactions · 0 assignees · Indexed Sep 15, 2026
Chisel Integration is Painful Open

feature request

chipsalliance/chisel#1445 · 2 comments · 1 reaction · 0 assignees · Indexed Sep 15, 2026
Need a way to turn on debug flag for treadle and verilator backend Open

chipsalliance/chisel#1447 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Bad error reporting on wrong (subword) assignments Open

good first issue

chipsalliance/chisel#1465 · 6 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
java.util.NoSuchElementException: None.get encountered in `HasId` Open

chipsalliance/chisel#1466 · 8 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
CloneModuleAsRecord needs a macro Open

chipsalliance/chisel#1478 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Using "Flipped" on singleton Bundle results in unexpected behavior Open

chipsalliance/chisel#1497 · 4 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Propose Binary operator for Bool and Bits. Open

chipsalliance/chisel#1503 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Interval literal creation is inconsistent Open

API Modification bug

chipsalliance/chisel#1507 · 3 comments · 0 reactions · 1 assignee · Indexed Sep 15, 2026
Does chisel plan to support full-featured SVA? Open

chipsalliance/chisel#1508 · 0 comments · 2 reactions · 0 assignees · Indexed Sep 15, 2026
Bundle asUInt ignores structural width Open

chipsalliance/chisel#1510 · 2 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Some recommendations on stop Open

chipsalliance/chisel#1521 · 4 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Printable should adopt a `f"`-like handling of `%` Open

chipsalliance/chisel#1522 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Static Right shift of SInt is inconsistent: neither arithmetic nor logical Open

chipsalliance/chisel#1528 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Add CONTRIBUTING.md Open

chipsalliance/chisel#1559 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
chisel emitts expensive verilog Open

chipsalliance/chisel#1564 · 2 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Vec.reduceTree leads to java.lang.OutOfMemoryError Open

chipsalliance/chisel#1576 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Why does FixedPoint get interpreted as Double when printing? Open

chipsalliance/chisel#1588 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Mixing ChiselStage with ChirrtlEmitter does not work in 3.4.0-RC2 Open

bug

chipsalliance/chisel#1592 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Get reset value from RegInit Open

chipsalliance/chisel#1599 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Cat() not returning a literal for literal inputs Open

chipsalliance/chisel#1632 · 2 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Bad Error when calling .asUInt on empty Bundle Open

bug

chipsalliance/chisel#1642 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026

chipsalliance/chisel

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