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chipsalliance

73 indexed repositories · View on GitHub

chisel
Chisel: A Modern Hardware Design Language

Scala · 4782 stars
rocket-chip
Rocket Chip Generator

Scala · 3865 stars
verible
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

C++ · 1936 stars
riscv-dv
Random instruction generator for RISC-V processor verification

Python · 1354 stars
Cores-VeeR-EH1
VeeR EH1 core

SystemVerilog · 966 stars
chisel-template
A template project for beginning new Chisel work

Shell · 708 stars
Surelog
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil...

C++ · 475 stars
Caliptra
Caliptra IP and firmware for integrated Root of Trust block

473 stars
f4pga
FOSS Flow For FPGA

Python · 449 stars
sv-tests
Test suite designed to check compliance with the SystemVerilog standard.

SystemVerilog · 394 stars
VeeRwolf
FuseSoC-based SoC for VeeR EH1 and EL2

Verilog · 343 stars
Cores-VeeR-EL2
VeeR EL2 Core

SystemVerilog · 343 stars
t1

Scala · 323 stars
f4pga-examples
Example designs showing different ways to use F4PGA toolchains.

Verilog · 289 stars
Cores-VeeR-EH2
VeeR EH2 core

SystemVerilog · 279 stars
UHDM
Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, ...

C++ · 269 stars
dromajo
RISC-V RV64GC emulator designed for RTL co-simulation

C++ · 244 stars
synlig
SystemVerilog synthesis tool

Verilog · 237 stars
silicon-notebooks

Jupyter Notebook · 177 stars
caliptra-sw
Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test

Rust · 167 stars
53 more repositories live on View on GitHub

Open All

3066 open issues indexed

mtvec handler code alignment needs to be configurable (#564) Open

chipsalliance/riscv-dv#574 · 3 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Map PMP regions to sections of the generated program Open

chipsalliance/riscv-dv#586 · 1 comment · 0 reactions · 2 assignees · Indexed Sep 15, 2026
Customizing the travis.yml configuration for pygen Open

chipsalliance/riscv-dv#597 · 8 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
PMP support for rv64gc in SV39 mode appears broken (for single & dual harts) Open

chipsalliance/riscv-dv#636 · 4 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
jump to an unexpected return address, unexpected instruction address_misaligned exception occurs Open

chipsalliance/riscv-dv#690 · 2 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
#727 issue not solved (Vector instruction stream SV randomization fails because of conflicting constraints) Open

chipsalliance/riscv-dv#737 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
PMP support for rv64gc dual harts in BARE mode appears broken Open

chipsalliance/riscv-dv#744 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
FPU L/S instructions data sections. Open

chipsalliance/riscv-dv#761 · 2 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Provide a small percentage of illegal Rounding Modes in fcsr. Open

chipsalliance/riscv-dv#768 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Continuing on error in run.py Open

chipsalliance/riscv-dv#774 · 3 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Jump to undefined label is generated for rv64gc riscv_hint_instr_test Open

chipsalliance/riscv-dv#776 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
some problems in csr_test Open

chipsalliance/riscv-dv#777 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Supported tests from testlist in pyflow Open

chipsalliance/riscv-dv#781 · 3 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Time to generate a test using pyflow Open

chipsalliance/riscv-dv#783 · 2 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Target: rv32imc_sv32, test: riscv_hint_instr_test - incorrect jump to undefined label is generated in UVM Open

chipsalliance/riscv-dv#792 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Store segfault riscv_load_store_rand_addr_instr_stream Open

chipsalliance/riscv-dv#793 · 2 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Target test: rv32imafdc, test: riscv_invalid_csr_test - UVM simulation fails because of the wrong constraints. Open

chipsalliance/riscv-dv#794 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Unimplemented CSR appears in the generated .S file Open

chipsalliance/riscv-dv#795 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 15, 2026
"illegal operands" and "already defined symbol" in generated .S test Open

chipsalliance/riscv-dv#796 · 2 comments · 1 reaction · 0 assignees · Indexed Sep 15, 2026
Spike simulator timeout Open

chipsalliance/riscv-dv#797 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
riscv_pmp_test does not work for rv32imc target Open

chipsalliance/riscv-dv#798 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
PTE permission bits not randomized for mmu stress test Open

chipsalliance/riscv-dv#800 · 0 comments · 3 reactions · 0 assignees · Indexed Sep 15, 2026
RV32E instruction set support Open

chipsalliance/riscv-dv#801 · 4 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
cannot generate riscv_csr_test. Open

chipsalliance/riscv-dv#805 · 3 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Infinite looping tests generated when PMP is enabled with user/supervisor mode Open

chipsalliance/riscv-dv#806 · 2 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
The "relocation truncated to fit" error occurs on a compilation of a code generated for the "ml" target. Open

chipsalliance/riscv-dv#807 · 3 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Use of kernel programs and how to enable Open

chipsalliance/riscv-dv#809 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 15, 2026
How to configure test to generate sequences with instruction, load and Store/Amo access fault for RV32IA Extension? Open

chipsalliance/riscv-dv#813 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Generated tests only utilize two privilege modes Open

chipsalliance/riscv-dv#821 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
--mabi ilp32 !! Open

chipsalliance/riscv-dv#823 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Is there any Zfinx support planned? Open

chipsalliance/riscv-dv#825 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
When the C_JALR instruction convert to bin format, we meet error. The rs1 should not be X0. Open

chipsalliance/riscv-dv#826 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Code is running fine, but, unable to see the waveforms Open

chipsalliance/riscv-dv#827 · 2 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
VCS Error Open

chipsalliance/riscv-dv#830 · 8 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Error after PR is merged Open

chipsalliance/riscv-dv#835 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
scripts.lib cannot be found Open

chipsalliance/riscv-dv#836 · 2 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Certificate OIDs Open

enhancement future

chipsalliance/Caliptra#32 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 15, 2026
HW Release Model - Collaterals Test Open

chipsalliance/Caliptra#63 · 3 comments · 0 reactions · 1 assignee · Indexed Sep 15, 2026
Create Caliptra TradeMark Approval Program Open

chipsalliance/Caliptra#174 · 0 comments · 0 reactions · 1 assignee · Indexed Sep 15, 2026
Doc inconsistency in UDS vs UDS seed Open

chipsalliance/Caliptra#191 · 3 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
SOC Ability to Independently Reset Caliptra Open

chipsalliance/Caliptra#201 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Fuse "IDEVID CERT IDEVID ATTR" and IDevID Certificate incomplete correlation, discrepancy and typo. Open

chipsalliance/Caliptra#205 · 3 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
powergood and CPTRA_OBF_KEY discrepancy and typo Open

chipsalliance/Caliptra#208 · 0 comments · 0 reactions · 1 assignee · Indexed Sep 15, 2026
Caliptra 2.0 FIPS requirements Open

Rev 2.0

chipsalliance/Caliptra#215 · 0 comments · 0 reactions · 2 assignees · Indexed Sep 15, 2026
Caliptra2.0 Support for multiple secure boot authentication keys Open

chipsalliance/Caliptra#220 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
How to generate obfuscation keys with ECO. Open

chipsalliance/Caliptra#221 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
wrap the non-scan flops in a dedicated hierarchy Open

chipsalliance/Caliptra#224 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
is there a table of verification tools used? Open

chipsalliance/Caliptra#238 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Incorrect grammar in 2.0 spec Open

Rev 2.0

chipsalliance/Caliptra#241 · 0 comments · 0 reactions · 1 assignee · Indexed Sep 15, 2026
Should Caliptra transition to the DebugUnlocked whenever the SoC enters the debug state, regardless of the product lifecycle state? Open

chipsalliance/Caliptra#252 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026

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