chipsalliance/Surelog

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SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

Stars: 475
Forks: 90
Open beginner issues: 0
Indexed issues: 47
Avg merge: 1h 39m
Merged PRs (30d): 37

Dominant language: C++
License: Apache-2.0
Last GitHub push: Sep 14, 2026
Latest indexed: Sep 14, 2026
Contributing guide: No contributing guide
Code of conduct: Code of conduct
Beginner labels: help wanted

Open All

47 open issues indexed

Parameters: more readable if either const reference or pointer. But no writable reference. Open

code-clean

chipsalliance/Surelog#41 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
A lot of standard functionality can benefit from using abseil Open

chipsalliance/Surelog#42 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Options: Make gnu conform: Make long options start with double-dash Open

chipsalliance/Surelog#68 · 4 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Don't attempt to run antlr if java-jre is not available Open

chipsalliance/Surelog#98 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Antlr4 warm-up times - can this be improved/pre-computed ? Open

chipsalliance/Surelog#117 · 9 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Errror report: line numbers are off Open

chipsalliance/Surelog#161 · 10 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Call with -nobuiltin will still pull in pre-compiled *.slpp and *.slpa (was: 'make install' fails) Open

chipsalliance/Surelog#177 · 6 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Publish API docs on readthedocs Open

documentation infra

chipsalliance/Surelog#305 · 8 comments · 1 reaction · 0 assignees · Indexed Sep 14, 2026
Add Surelog AST->UHDM SystemVerilog Constraints support Open

chipsalliance/Surelog#315 · 2 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Schematic diagrams Open

chipsalliance/Surelog#338 · 22 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Trailing comma in port-list results in hard-to-understand error message Open

chipsalliance/Surelog#366 · 8 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Setup verismith to run against Surelog Open

chipsalliance/Surelog#865 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
"this" statement is not stored properly Open

chipsalliance/Surelog#938 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Add stack trace dump backward-cpp support to Surelog Open

help wanted

chipsalliance/Surelog#1639 · 13 comments · 0 reactions · 1 assignee · Indexed Sep 14, 2026
Backward/Forward Compatibility Open

chipsalliance/Surelog#1707 · 12 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
n2 function in ParseFile.cpp Open

chipsalliance/Surelog#1779 · 0 comments · 0 reactions · 1 assignee · Indexed Sep 14, 2026
Swap out posix calls for standard equivalent Open

code-clean enhancement

chipsalliance/Surelog#1839 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Fix ArianeElab2 test issue with default tag assign Open

chipsalliance/Surelog#2100 · 3 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Investigate use of precompiled headers Open

help wanted infra

chipsalliance/Surelog#2364 · 2 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Source code comments not available in non-elaborated model Open

chipsalliance/Surelog#2698 · 4 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Track (and expose) bindings post elaboration Open

chipsalliance/Surelog#2847 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Inconsistent use of typespecs with parameters Open

chipsalliance/Surelog#2888 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Inconsistent typespec for localparams Open

chipsalliance/Surelog#2952 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Remove variables::VpiSigned? Open

chipsalliance/Surelog#2953 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Duplicate variables in function Open

chipsalliance/Surelog#2954 · 4 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Add IWYU build to CI Open

enhancement infra

chipsalliance/Surelog#2981 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Food for thought: SymbolId can carry a pointer to the owning SymbolTable Open

chipsalliance/Surelog#3054 · 15 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Selectively disable printing chosen warnings Open

chipsalliance/Surelog#3108 · 0 comments · 1 reaction · 0 assignees · Indexed Sep 14, 2026
Deep recursion when running LoopParamOver test ? Open

chipsalliance/Surelog#3146 · 7 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Coverage report is broken Open

chipsalliance/Surelog#3190 · 2 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Missing interface_array (follow up to PR #3101) Open

chipsalliance/Surelog#3198 · 7 comments · 0 reactions · 1 assignee · Indexed Sep 14, 2026
Bogus error message Open

chipsalliance/Surelog#3239 · 4 comments · 0 reactions · 1 assignee · Indexed Sep 14, 2026
Undefined behavior shift in CompileHelper.cpp Open

chipsalliance/Surelog#3376 · 11 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Delay is wrongly treated as IntConst Open

chipsalliance/Surelog#3447 · 7 comments · 0 reactions · 1 assignee · Indexed Sep 14, 2026
FindANTLR.cmake: should also look in `$CLASSPATH` Open

chipsalliance/Surelog#3551 · 3 comments · 0 reactions · 1 assignee · Indexed Sep 14, 2026
Set of exposed internal API is very wide. Impossible to guarantee stable API long term. Open

chipsalliance/Surelog#3568 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Surelog (library) leaks memory. Open

chipsalliance/Surelog#3661 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 14, 2026
incorrect variable capture in uhdm Open

chipsalliance/Surelog#3718 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Whether to reduce or not, elaborated vs. non-elaborated Open

chipsalliance/Surelog#3759 · 2 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
-defer, -link does not respect package ordering during compilation/elaboration (-link) Open

chipsalliance/Surelog#3846 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Identifying `reg` type in UHDM model Open

chipsalliance/Surelog#3893 · 6 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Incorrect cmake installation instructions fail to install files into the stage directory Open

chipsalliance/Surelog#3963 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
surelog fails to create package files pkg/work/uvm_pkg.sv.slpp, pkg/work/uvm_pkg.sv.slpp, pkg/work/uvm_pkg.sv.slpp, pkg/work/uvm_pkg.sv.slpp Open

chipsalliance/Surelog#3965 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 14, 2026
9 tests fail: Fatal Python error: PyEval_AcquireThread: the function must be called with the GIL held, but the GIL is released (the current Python thread state is NULL) Open

chipsalliance/Surelog#3971 · 2 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Convert structs into additional ports Open

chipsalliance/Surelog#4021 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Build process finds wrong Python when using pyenv on Mac Open

chipsalliance/Surelog#4036 · 2 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Surelog build failures on v1.85 and v1.86 Open

chipsalliance/Surelog#4064 · 3 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026

chipsalliance/Surelog

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