Identifying `reg` type in UHDM model

There doesn't seem to be a way to identify `reg` type in UHDM model. The type is modeled as `logic_typespec` but there's nothing in the model to differentiate it with regular `logic` type.

```
module top ();
reg a = 0;
endmodule
```

https://github.com/chipsalliance/Surelog/blob/d5f0e268c75076b6c41cc5d7e7072bbda37b35b9/src/DesignCompile/CompileType.cpp#L1094-L1108

Start in src/DesignCompile/CompileType.cpp at lines 1094-1108 and inspect how the example `reg a = 0;` becomes a `logic_typespec` in the UHDM model. Compare that representation with regular `logic` and determine what model information is needed to distinguish them. Done means the UHDM model can identify the `reg` type separately.

Written by the indexing model from the issue text.