chipsalliance / chipsalliance/Surelog
Trailing comma in port-list results in hard-to-understand error message
- Dominant language
- C++
- Stars
- 475
- Forks
- 90
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- 1h 39m
- Merged PRs (30d)
- 37
Description
Here is an example of a common mistake (as it should be allowed in the language in the first place), an extra comma at the end of a port-list:
```verilog
module foo(
input a,
);
endmodule
```
The resulting error message is hard to understand:
```
[SYNTX:PA0207] t.sv:3: Syntax error: mismatched input ')' expecting {'.', 'interface', 'virtual', 'type', 'input', 'output', 'inout', 'ref', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', DOLLAR_UNIT, '(*', 'this', DOLLAR_ROOT, 'randomize', 'sample', Escaped_identifier, Simple_identifier},
);
^-- ./slpp_all/work/t.sv:3:0:.
```
Similar for parameters
```verilog
module foo #(
parameter integer FOO=42,
)();
endmodule
```
The resulting syntax error is also not easy to understand:
```
[SYNTX:PA0207] t.sv:3: Syntax error: no viable alternative at input 'module foo #(\n parameter integer FOO=42,\n)',
)();
^-- ./slpp_all/work/t.sv:3:0:.
```
I suggest to allow the trailing comma in the parser and then just report it one level up. We can report a syntax error there.
(we should maybe support some gentle syntax extensions to SystemVerilog: it should actually be allowed to have a trailing comma, and it should be recommended practice in SV programming, once we get the standard changed :)
This can be implemented by having the above a simple warning instead of error but still go on with the rest of processing).
Contributor guide
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Research direction
No files or tests are named. Start by locating the parser rules for port-lists and parameter lists and the diagnostic path that emits PA0207; reproduce both SystemVerilog examples, then verify trailing commas are handled with the intended clearer diagnostic or warning while processing continues.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- cpp
- Domain
- compilers
- Issue type
- Feature
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 35/100