Delay is wrongly treated as IntConst

Example:
```
module main;
parameter p_dly = 0;
wire a, b;
assign #p_dly a = b;
endmodule
```

Uhdm output:
```
|vpiContAssign:
\_cont_assign: , line:4:17, endln:4:22
|vpiParent:
\_module_inst: work@main (work@main), file:abc.v, line:1:1, endln:5:10
|vpiDelay:
\_constant: , line:4:10, endln:4:16
|vpiDecompile:p_dly
|vpiSize:64
|UINT:0
|vpiConstType:9
```

Note that the non-numeric delay is being parsed as a number.

The issue is from the following snippet where delay_value is assumed to be an IntConst which isn't true as per the grammar.
https://github.com/chipsalliance/Surelog/blob/909e2bd9783f4ecf6e7130415b5d0cf12adf71ca/src/SourceCompile/SV3_1aTreeShapeListener.cpp#L854-L864

https://github.com/chipsalliance/Surelog/blob/909e2bd9783f4ecf6e7130415b5d0cf12adf71ca/grammar/SV3_1aParser.g4#L1000-L1008

Following tests are impacted by this issue -
* LibraryIntercon
* Icarus (sched1.v)
* Unisim (ISERDES.v)