chipsalliance / chipsalliance/Surelog
Schematic diagrams
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- C++
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Description
Hey -
I am attempting to build a schematic diagram visualizer tool for UHDM designs. To keep the scope small, layout of individual components is decided to be out of scope, at least for now. However, I still need to implement logic to identify higher level blocks like FF, Adders, Latch, etc. AFAIK, neither UHDM nor vpi provide such information. Just wondering if there's any work happening along this line or are there any examples of how build this on top of UHDM (or vpi).
Appreciate your continued support.
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