chipsalliance / chipsalliance/Surelog
Setup verismith to run against Surelog
Open
- Dominant language
- C++
- Stars
- 475
- Forks
- 90
- Avg merge
- 1h 39m
- Merged PRs (30d)
- 37
Description
https://github.com/ymherklotz/verismith
> Verilog Fuzzer to test the major simulators and synthesisers by generating random, valid Verilog.
Contributor guide
No contributing guide indexed for this repository
Research direction
No Surelog file, test, or entry point is identified. Start by reviewing the linked Verismith project and the boundary where it would run against Surelog; done means Verismith can execute Surelog as one of its tested tools.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- cpp
- Domain
- compilers, testing-qa
- Issue type
- Feature
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 25/100