chipsalliance / chipsalliance/Surelog
Add Surelog AST->UHDM SystemVerilog Constraints support
Open
- Dominant language
- C++
- Stars
- 475
- Forks
- 90
- Avg merge
- 1h 39m
- Merged PRs (30d)
- 37
Description
Populate UHDM with all the SystemVerilog constraints objects from the Surelog AST and internal (new) datastructures.
Related to issue: https://github.com/alainmarcel/UHDM/issues/185
Contributor guide
No contributing guide indexed for this repository
Research direction
Start by reading related issue 185 and tracing how the Surelog AST and internal data structures currently populate UHDM. Identify the constraint objects that are in scope and define completion as supporting all SystemVerilog constraint objects named by the issue.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- cpp
- Domain
- compilers
- Issue type
- Feature
- Difficulty
- 5/5
- Estimated time
- Over a week
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 20/100