chipsalliance / chipsalliance/Surelog
Inconsistent typespec for localparams
- Dominant language
- C++
- Stars
- 475
- Forks
- 90
- Avg merge
- 1h 39m
- Merged PRs (30d)
- 37
Description
Input:
```
package riscv;
localparam XLEN = 64;
localparam VLEN = (XLEN == 32) ? 32 : 64;
endpackage
```
Output:
```
|uhdmallPackages:
\_package: riscv (riscv::), id:72 test.sv:1:1: , endln:4:11, parent:unnamed, parID:71
|vpiName:riscv
|vpiFullName:riscv::
|vpiParameter:
\_parameter: (riscv::XLEN), id:40, line:2:14, endln:2:18, parent:riscv::, parID:72
|UINT:64
|vpiTypespec:
\_int_typespec: , id:47
|vpiLocalParam:1
|vpiName:XLEN
|vpiFullName:riscv::XLEN
|vpiParameter:
\_parameter: (riscv::VLEN), id:49, line:3:14, endln:3:18, parent:riscv::, parID:72
|vpiLocalParam:1
|vpiName:VLEN
|vpiFullName:riscv::VLEN
|vpiParamAssign:
\_param_assign: , id:42, line:2:14, endln:2:23, parent:riscv::, parID:72
|vpiRhs:
\_constant: , id:46, line:2:21, endln:2:23
|vpiDecompile:64
|vpiSize:32
|UINT:64
|vpiTypespec:
\_int_typespec: , id:47
|vpiConstType:9
|vpiLhs:
\_parameter: (riscv::XLEN), id:40, line:2:14, endln:2:18, parent:riscv::, parID:72
|vpiParamAssign:
\_param_assign: , id:56, line:3:14, endln:3:43, parent:riscv::, parID:72
|vpiRhs:
\_operation: , id:68, line:3:21, endln:3:43
|vpiOpType:32
|vpiOperand:
\_operation: , id:66, line:3:22, endln:3:32, parID:68
|vpiOpType:14
|vpiOperand:
\_ref_obj: (XLEN), id:65, line:3:22, endln:3:26, parID:66
|vpiName:XLEN
|vpiActual:
\_parameter: (riscv::XLEN), id:40, line:2:14, endln:2:18, parent:riscv::, parID:72
|vpiOperand:
\_constant: , id:67, line:3:30, endln:3:32, parID:66
|vpiDecompile:32
|vpiSize:64
|UINT:32
|vpiConstType:9
|vpiOperand:
\_constant: , id:69, line:3:36, endln:3:38, parID:68
|vpiDecompile:32
|vpiSize:64
|UINT:32
|vpiConstType:9
|vpiOperand:
\_constant: , id:70, line:3:41, endln:3:43, parID:68
|vpiDecompile:64
|vpiSize:64
|UINT:64
|vpiConstType:9
|vpiLhs:
\_parameter: (riscv::VLEN), id:49, line:3:14, endln:3:18, parent:riscv::, parID:72
|vpiDefName:riscv
```
Note that first `localparam` has a `int_typespec` but the second one has none. Also, this is non-elaborated out and the input doesn't explicitly declare the type so the first declaration shouldn't have one either.
Contributor guide
No contributing guide indexed for this repository
Research direction
Start by reproducing the provided SystemVerilog package and comparing the UHDM output for XLEN and VLEN. Trace localparam type-specification handling in the parser, elaborator, or UHDM construction path, then check existing tests for package parameters. Done means both non-explicitly typed localparams receive consistent typespec metadata matching the expected non-elaborated output.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- cpp
- Domain
- compilers
- Issue type
- Bug
- Difficulty
- 3/5
- Estimated time
- 1-2 days
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 35/100