chipsalliance / chipsalliance/Surelog
Bogus error message
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Description
@hs-apotell this new error message is incorrect:
https://github.com/chipsalliance/Surelog/blob/b4ad3fc02ef02ad162f34ac7d18c397e5fd6e9d9/src/Design/FileContent.cpp#L689
The testcase black-parrot has indeed statements that cross files (Due to includes).
Please remove that check. It is not compliant with Verilog proprocessing.
The issue is discussed here, it is a sub-issue of that case:
https://github.com/antmicro/yosys-systemverilog/issues/1064#issuecomment-1255237701
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