chipsalliance/UHDM
View on GitHubUniversal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
- Stars
- 269
- Forks
- 48
- Open beginner issues
- 0
- Indexed issues
- 14
- Avg merge
- 2h 22m
- Merged PRs (30d)
- 16
- Dominant language
- C++
- License
- Apache-2.0
- Last GitHub push
- Sep 13, 2026
- Latest indexed
- Sep 14, 2026
- Contributing guide
- No contributing guide
- Code of conduct
- Code of conduct
- Beginner labels
- No beginner labels indexed
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chipsalliance/UHDM#40 · 2 comments · 0 reactions · 0 assignees ·
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Generate dot file Openenhancement
chipsalliance/UHDM#73 · 6 comments · 0 reactions · 0 assignees ·
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documentation
chipsalliance/UHDM#74 · 2 comments · 0 reactions · 0 assignees ·
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chipsalliance/UHDM#77 · 2 comments · 0 reactions · 1 assignee ·
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chipsalliance/UHDM#178 · 1 comment · 0 reactions · 1 assignee ·
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chipsalliance/UHDM#185 · 1 comment · 0 reactions · 0 assignees ·
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chipsalliance/UHDM#207 · 4 comments · 0 reactions · 0 assignees ·
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enhancement
chipsalliance/UHDM#319 · 24 comments · 0 reactions · 0 assignees ·
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chipsalliance/UHDM#498 · 1 comment · 0 reactions · 0 assignees ·
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chipsalliance/UHDM#783 · 1 comment · 0 reactions · 0 assignees ·
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chipsalliance/UHDM#902 · 1 comment · 0 reactions · 0 assignees ·
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chipsalliance/UHDM#1080 · 1 comment · 0 reactions · 0 assignees ·
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chipsalliance/UHDM#1101 · 5 comments · 0 reactions · 0 assignees ·
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chipsalliance/UHDM#1102 · 1 comment · 1 reaction · 0 assignees ·