variable_drivers_group and variable_loads_group reject my loads() and drivers() assignment.

I am working on traversing the design and setting the loads() and drivers() for nets and variables.
Since this is not already currently supported (see issue #1101).

I keep getting messages of the form:
```
Internal Error: adding wrong object type (assignment) in a variable_loads_group group!
Internal Error: adding wrong object type (assignment) in a variable_drivers_group group!
```

Surelog represents variable assignments as UHDM::assignment which isn't listed in the list of possibilities

I am also having issues with other procedural statement like for_loop, if_statement, while_loop, etc
All of those statements have the ability to be a load or a driver for a variable.
I would prefer to report the statement itself as the load or driver instead of the different assignment/expressions that are created for those statements.

I also wonder why I see things like cont_assign and cont_assign_bit in [variable_loads_group.yaml](https://github.com/chipsalliance/UHDM/blob/master/model/variable_loads_group.yaml) and [variable_drivers_group.yaml](https://github.com/chipsalliance/UHDM/blob/master/model/variable_drivers_group.yaml). I understand they should be there for nets but I don't think they are appropriate for variables (please correct me if I am wrong). I think those 2 files need some updates.

As a side question, what do I need to do to rebuild the generated files if I modify the model? Running cmake --build . is not updating the generated folder with my changes.

Start with variable_loads_group.yaml and variable_drivers_group.yaml, then inspect the generated folder and the project’s model-generation or build instructions. Determine how assignment, for_loop, if_statement, and while_loop objects should be represented for variable loads and drivers, and verify that model changes regenerate the affected files.

Written by the indexing model from the issue text.