chipsalliance/VeeRwolf

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FuseSoC-based SoC for VeeR EH1 and EL2

Stars: 343
Forks: 75
Open beginner issues: 0
Indexed issues: 22

Dominant language: Verilog
License: No license data
Last GitHub push: Dec 11, 2024
Latest indexed: Sep 15, 2026
Contributing guide: No contributing guide
Code of conduct: Code of conduct
Beginner labels: No beginner labels indexed
PR merge metrics: No merged PRs in 30d

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22 open issues indexed

Zephyr with adxl362 fails to compile Open

chipsalliance/VeeRwolf#14 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Unsupported board in build Zephyr applications Open

chipsalliance/VeeRwolf#21 · 6 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
verilator + openocd + gdb simulation issue Open

chipsalliance/VeeRwolf#25 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
debugging is not working !!! Open

chipsalliance/VeeRwolf#26 · 12 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
bscan_tap module - how does it work? Open

chipsalliance/VeeRwolf#29 · 21 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Swerv configuration & Swervolf Open

chipsalliance/VeeRwolf#30 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Fusesoc Simulation Error Open

chipsalliance/VeeRwolf#31 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Do you have any plan to support SweRV-EH2. Open

chipsalliance/VeeRwolf#37 · 2 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
fusesoc run --target=nexys_a7 swervolf with Vivado 2020.1 Open

chipsalliance/VeeRwolf#39 · 2 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
fusesoc run --target=sim swervolf with Verilator=3.918 Open

chipsalliance/VeeRwolf#40 · 2 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
ERROR: [Labtools 27-3165] End of startup status: LOW when [ run --target=nexys_a7 --flag=cpu_el2 swervolf] Open

chipsalliance/VeeRwolf#43 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
[Nexys4 DDR] Struggling to load into ICCM (address 0xEE000000) Open

chipsalliance/VeeRwolf#46 · 3 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
fusesoc run --target=basys3 with vivado 2021.2 Open

chipsalliance/VeeRwolf#51 · 5 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
axi/wb bus cycle times Open

chipsalliance/VeeRwolf#55 · 7 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Tested/Implemented on other cores Open

chipsalliance/VeeRwolf#58 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Read access stops when read/write access is repeated Open

chipsalliance/VeeRwolf#59 · 2 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Error when building Zephyr example Open

chipsalliance/VeeRwolf#63 · 3 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Assertion error when running fusesoc simulation Open

chipsalliance/VeeRwolf#67 · 6 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
May I ask how to generate the build. h file used for FPGA project？ Open

chipsalliance/VeeRwolf#68 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Error in Build of Predefined examples of Zephyr Open

chipsalliance/VeeRwolf#69 · 2 comments · 1 reaction · 0 assignees · Indexed Sep 15, 2026
VeeRwolf build issue Open

chipsalliance/VeeRwolf#78 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
How to program both of FPGA bit file and SW binary code into SPI serial flash ? Open

chipsalliance/VeeRwolf#79 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026

chipsalliance/VeeRwolf

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