chipsalliance / chipsalliance/VeeRwolf
bscan_tap module - how does it work?
Open
- Dominant language
- Verilog
- Stars
- 343
- Forks
- 75
- PR merge metrics
- No merged PRs in 30d
Description
Hi Olof,
I'm new in FPGAs and wondering how does your bscan_tap module work ? where are the definitions / descriptions of the BSCAN2 modules? How are some internal wires driven?
Thanks in advance
Alex
Contributor guide
No contributing guide indexed for this repository
Assessment
This issue has not been assessed yet.