axi/wb bus cycle times

I have your design running in nexys A7 with an EL2 core.

When I do a sequence of writes to an I/O port, such as GPIO, and my code is running in ICCM, the writes are lost, except for the last one. I can solve the problem by inserting some delay in between the I/O writes.

It appears that with optimized code, the writes through Axi / Axi Mux / WB occur slower than the processor can write the data.

Is this the way it is supposed to work? Is there some sort of mechanism for the AXI writes to delay the processor core while each one is completing?

I guess I can write code to wait on I/O writes to complete before I send another one. Am I required to do that?

Start by tracing the AXI / AXI Mux / Wishbone path used by EL2 when issuing consecutive GPIO writes from ICCM. Reproduce the sequence on a Nexys A7 and determine whether each write provides completion back to the processor. Done means the expected write ordering and required waiting behavior are established and documented or corrected.

Written by the indexing model from the issue text.