chipsalliance / chipsalliance/VeeRwolf

[Nexys4 DDR] Struggling to load into ICCM (address 0xEE000000)

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Description

Hi all,

I've been interested in running some tests on the SweRVolf, and have been succesfully programming it within the RAM region (0x00000000-0x07FFFFFF) and the DCCM region (0xF0040000-0xF004FFFF).

However, as I understand the EH1 core also has a memory region called "ICCM" for fast instruction access, at (0xEE000000-0xEE00FFFF).

The DCCM works quite well: Infact I've already got some figures for the memory bandwidth:

code in RAM, data in RAM: read @ 21.5MB/s, write @ 25MB/s
code in RAM, data in DCCM: read @ 136MB/s, write @ 136MB/s

(p.s. not sure why RAM is slower to read than to write, but anyway...)

What I'd like to do now is to put my code into ICCM - but I'm having issues loading it. Here is my gdb input:
```
(gdb) tar rem :3333
Remote debugging using :3333
_finish () at crt0.s:32
32 beq x0, x0, _finish
(gdb) load
Loading section .text.init, size 0x30 lma 0x10000
Loading section .text, size 0x812 lma 0x10030
Loading section .data, size 0xaf lma 0x20000
Loading section .text.iccm, size 0x1a lma 0xee000000
Start address 0x00010000, load size 2315
Transfer rate: 10 KB/sec, 578 bytes/write.
(gdb)
```

And here are the OpenOCD errors that I see after issuing the `load` gdb command:
```
Info : accepting 'gdb' connection on tcp/3333
Error: Target riscv.cpu: Failed to write memory (addr=0xee000000)
Error: progbuf=disabled, sysbus=disabled, abstract=failed
```

If I try memory dumping the location, I get
```
(gdb) x/8x 0xee000000
0xee000000 : 0x00000000 0x00000000 0x00000000 0x00000000
0xee000010 : 0x00000000 0x00000000 0x00000000 0x00000000
```
and OpenOCD also spews out more errors at me:
```
Error: Target riscv.cpu: Failed to read memory (addr=0xee000000)
Error: progbuf=disabled, sysbus=disabled, abstract=failed
Error: Target riscv.cpu: Failed to read memory (addr=0xee000004)
Error: progbuf=disabled, sysbus=disabled, abstract=failed
...(trimmed)...
Error: Target riscv.cpu: Failed to read memory (addr=0xee00001c)
Error: progbuf=disabled, sysbus=disabled, abstract=failed
```

The OpenOCD launch command is `openocd -f swervolf_nexys_debug.cfg` and the `swervolf_nexys_debug.cfg` is the default one supplied with the repo (md5sum: `af7ea2b7922e9b34f8e578c18bbccfbd`)

`openocd --version` report: (p.s. Ignore the `bb96dc521` - that is my commit to fix the texinfo documentation build on my old ubuntu. the actual last meaningful commit is `5215fc52a Fix flashing on HiFive1. (#649)`)
```
Open On-Chip Debugger 0.11.0+dev-02000-gbb96dc521 (2021-10-08-15:57)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
```

Any ideas? I'm pretty sure there is an ICCM present, because if I look into the following file in the core build directory (`build/swervolf_0.7.4/nexys_a7-vivado/config/common_defines.vh`), I find
```
...(stripped output)...
`define RV_ICCM_SADR 32'hee000000
`define RV_ICCM_OFFSET 10'he000000
`define RV_ICCM_BANK_BITS 3
`define RV_ICCM_INDEX_BITS 14
`define RV_ICCM_SIZE_512
`define RV_ICCM_EADR 32'hee07ffff
`define RV_ICCM_ROWS 16384
`define RV_ICCM_NUM_BANKS 8
`define RV_ICCM_RESERVED 'h1000
`define RV_ICCM_SIZE 512
`define RV_ICCM_NUM_BANKS_8
`define RV_ICCM_BITS 19
`define RV_ICCM_REGION 4'he
`define RV_ICCM_DATA_CELL ram_16384x39
```

So it's definitely at 0xee000000, and it should be present, but I'm struggling to load into it. Should I be manually enabling the ICCM?

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