chipsalliance / chipsalliance/VeeRwolf
fusesoc run --target=sim swervolf with Verilator=3.918
- Dominant language
- Verilog
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- 343
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- 75
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Description
%Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lib/beh_lib.sv:403: Define or directive not defined: `RV_BTB_ADDR_HI
%Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lib/beh_lib.sv:403: Define or directive not defined: `RV_BTB_BTAG_SIZE
%Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lib/beh_lib.sv:418: Define or directive not defined: `RV_BTB_ADDR_HI
%Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lib/beh_lib.sv:418: syntax error, unexpected ':', expecting TYPE-IDENTIFIER
%Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lib/beh_lib.sv:418: Define or directive not defined: `RV_BTB_ADDR_LO
%Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lib/beh_lib.sv:421: Define or directive not defined: `RV_BTB_ADDR_HI
%Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lib/beh_lib.sv:421: Define or directive not defined: `RV_BTB_ADDR_LO
%Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lib/beh_lib.sv:421: Define or directive not defined: `RV_BTB_INDEX1_HI
%Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lib/beh_lib.sv:421: Define or directive not defined: `RV_BTB_INDEX1_LO
%Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lib/beh_lib.sv:424: Define or directive not defined: `RV_BTB_INDEX2_HI
%Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lib/beh_lib.sv:424: Define or directive not defined: `RV_BTB_INDEX2_LO
%Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lib/beh_lib.sv:427: Define or directive not defined: `RV_BTB_INDEX3_HI
%Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lib/beh_lib.sv:427: Define or directive not defined: `RV_BTB_INDEX3_LO
%Error: Exiting due to too many errors encountered; --error-limit=50
%Error: Command Failed /tools/verilator/3.918/bin/verilator_bin -f swervolf_0.7.3.vc --trace -Wno-fatal
Makefile:16: recipe for target 'Vswervolf_core_tb.mk' failed
make: *** [Vswervolf_core_tb.mk] Error 10
ERROR: Failed to build ::swervolf:0.7.3 : 'make' exited with an error code
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