chipsalliance / chipsalliance/VeeRwolf
Tested/Implemented on other cores
Open
- Dominant language
- Verilog
- Stars
- 343
- Forks
- 75
- PR merge metrics
- No merged PRs in 30d
Description
Hello. Is this implementation tested or planned to be tested on other Xilinx FPGA cores?
Contributor guide
No contributing guide indexed for this repository
Research direction
Start by reviewing the VeeR EH1 and EL2 support described in the repository and identifying which other Xilinx FPGA cores are in scope. Determine whether testing or implementation is expected; the issue is complete only when the supported cores and corresponding test status are established.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot
- Issue type
- Feature
- Difficulty
- 5/5
- Estimated time
- Over a week
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 20/100