debugging is not working !!!

I am following the 'debugging' sequences.
In normal simulation, "SweRV+FuseSoC rocks" is displayed.
But, in debug mode, there is no response from simulator after "releasing reset" message.
Please check the simulation results, as below,
Thanks in advance.

**[test sequences]**
- in terminal A
fusesoc run --target=sim --run swervolf --jtag_vpi_enable
- in terminal B
openocd -f $SWERVOLF_ROOT/data/swervolf_sim.cfg
- in terminal C
telnet localhost 4444

**[terminal message output]**
**- in terminal A**
INFO: Running
INFO: Running simulation
Starting jtag_vpi server: interface 127.0.0.1 (loopback), port 5555/tcp ...
jtag_vpi server created.
Waiting for client connection...
Client connection accepted.
JTAG VPI enabled. Not loading RAM
Releasing reset

**- in terminal B**
Open On-Chip Debugger 0.10.0+dev-01402-gccb21ab5a (2020-10-20-17:21)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
Info : only one transport option; autoselect 'jtag'
Info : Set server port to 5555
Info : Set server address to 127.0.0.1
Warn : `riscv set_prefer_sba` is deprecated. Please use `riscv set_mem_access` instead.
Info : Connection to 127.0.0.1 : 5555 succeed
Info : This adapter doesn't support configurable speed
Info : JTAG tap: riscv.cpu tap/device found: 0x00000001 (mfg: 0x000 (), part: 0x0000, ver: 0x0)
Info : datacount=2 progbufsize=0
Warn : We won't be able to execute fence instructions on this target. Memory may not always appear consistent. (progbufsize=0, impebreak=0)
Info : Examined RISC-V core; found 1 harts
Info : hart 0: XLEN=32, misa=0x40001104
Info : starting gdb server for riscv.cpu on 3333
Info : Listening on port 3333 for gdb connections
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections
Info : accepting 'telnet' connection on tcp/4444

**- in terminal C**
Trying 127.0.0.1...
Connected to localhost.
Escape character is '^]'.
Open On-Chip Debugger
> load_image /home/kdlee/work/riscv/chipsalliance/Cores-SweRVolf/sw/hello.elf
69 bytes written at address 0x00000000
downloaded 69 bytes in 4.572055s (0.015 KiB/s)

> reg pc 0
pc (/32): 0x00000000

> resume
>

Reproduce the sequence using the FuseSoC command, data/swervolf_sim.cfg, OpenOCD, telnet, and sw/hello.elf described in the report. Compare normal and debug-mode simulator output, then inspect the JTAG VPI and reset/resume path to locate where execution stops. Done means the debug sequence resumes the simulator and produces the expected response.

Written by the indexing model from the issue text.