chipsalliance / chipsalliance/VeeRwolf

verilator + openocd + gdb simulation issue

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Dominant language
Verilog
Stars
343
Forks
75
PR merge metrics
No merged PRs in 30d

Description

I have some problem when running simulation with "verilator+openocd+gdb".
'step' or 'continue' command in gdb do not work well. (there is no next gdb prompt after the commands)
I don't know what the problem is.
Please help me.

Actually, I run the test as below,
- run simulation in terminal A
fusesoc run --target=sim swervolf --jtag_vpi_enable
- run openocd in terminal B
openocd -f $SWERVOLF_ROOT/data/swervolf_sim.cfg
- run gdb in terminal C (hello.elf is build in sw folder)
riscv64-unknown-elf-gdb ./hello.elf
- gdb commands
(gdb) set remotetimeout 50000
(gdb) target remote localhost:3333
(gdb) load
(gdb) s
--> no response forever

Thank you.

Contributor guide

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Research direction

Reproduce the three-terminal setup using `fusesoc run --target=sim swervolf --jtag_vpi_enable`, `data/swervolf_sim.cfg`, and `riscv64-unknown-elf-gdb ./hello.elf`. Start by checking where `target remote`, `load`, and `s` stop responding; done means GDB returns to its prompt after these commands during the Verilator/OpenOCD simulation.

Written by the indexing model from the issue text.

Assessment

Domain
devtools, embedded-iot
Issue type
Bug
Difficulty
4/5
Estimated time
3-5 days
Activity status
Stale
Clarity
Needs clarification
Newbie friendliness
25/100

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