Fusesoc Simulation Error

**$ fusesoc run --target=sim swervolf**
INFO: Preparing ::cdc_utils:0.1
INFO: Downloading fusesoc/cdc_utils from github
INFO: Preparing chipsalliance.org:cores:SweRV_EH1:1.8
INFO: Downloading chipsalliance/Cores-SweRV from github
INFO: Preparing fusesoc:utils:generators:0.1.5
INFO: Downloading fusesoc/fusesoc-generators from github
INFO: Preparing ::jtag_vpi:0-r5
INFO: Downloading fjullien/jtag_vpi from github
INFO: Preparing pulp-platform.org::common_cells:1.16.4
INFO: Downloading pulp-platform/common_cells from github
INFO: Preparing ::simple_spi:1.6.1
INFO: Downloading olofk/simple_spi from github
INFO: Preparing ::uart16550:1.5.5-r1
INFO: Downloading olofk/uart16550 from github
INFO: Preparing ::verilog-arbiter:0-r3
INFO: Downloading bmartini/verilog-arbiter from github
INFO: Preparing ::wb_common:1.0.3
INFO: Downloading fusesoc/wb_common from github
INFO: Preparing pulp-platform.org::axi:0.23.0-r1
INFO: Downloading pulp-platform/axi from github
INFO: Preparing ::wb_intercon:1.2.2-r1
INFO: Downloading olofk/wb_intercon from github
INFO: Preparing ::swervolf:0.7.2
INFO: Generating ::swervolf-intercon:0.7.2
**ERROR: Setup failed : "python3 E:\cygwin64\home\Hamza\.cache\fusesoc\pulp-platform.org__axi_0.23.0-r1\scripts/axi_intercon_gen.py E:\cygwin64\home\Hamza\.cache\fusesoc\generated\swervolf-intercon_0.7.2\i
ntercon_input.yml" exited with an error code. See stderr for details.**

I'm using Cygwin terminal inside windows 10.
My Versions :
FuseSoC :1.11.0
Python : 3.6.4 ( Tried 3.9.1 as well )

I've tried virtual Environments aswell but I am still facing this same Issue.

Kindly help.

Start by rerunning `fusesoc run --target=sim swervolf` in the reported Cygwin environment and capture the missing stderr output. Inspect `scripts/axi_intercon_gen.py` and the generated `intercon_input.yml`; done means the AXI interconnect generation completes and the simulation target proceeds without the setup error.

Written by the indexing model from the issue text.