chipsalliance/sv-tests

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Test suite designed to check compliance with the SystemVerilog standard.

Stars: 394
Forks: 103
Open beginner issues: 0
Indexed issues: 47

Dominant language: SystemVerilog
License: ISC
Last GitHub push: Aug 6, 2026
Latest indexed: Sep 14, 2026
Contributing guide: No contributing guide
Code of conduct: Code of conduct
Beginner labels: good first issue
PR merge metrics: No merged PRs in 30d

Open All

47 open issues indexed

Allow testing of multiple versions of the same tool. Open

chipsalliance/sv-tests#34 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Parse the error message Open

chipsalliance/sv-tests#35 · 6 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Naming of tests should contain short synopsis of what is tested Open

tests

chipsalliance/sv-tests#46 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Specification of language standard Open

enhancement runners tests

chipsalliance/sv-tests#317 · 2 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Add Sphinx documentation and publish at sv-tests.rtfd.io Open

documentation

chipsalliance/sv-tests#327 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Add s80x86 as a test Open

import-testsuite tests

chipsalliance/sv-tests#332 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Tag tests with parts of a SystemVerilog frontend required Open

chipsalliance/sv-tests#333 · 2 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Look at cloudbuild as a potential CI system? Open

chipsalliance/sv-tests#429 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Suggested README updates Open

documentation good first issue

chipsalliance/sv-tests#444 · 2 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Suggested runner usability enhancements Open

enhancement runners

chipsalliance/sv-tests#445 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Runner tracking of expected pass/fails Open

enhancement runners

chipsalliance/sv-tests#446 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Add test for var in port-list Open

good first issue tests

chipsalliance/sv-tests#486 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Add a @(posedge 1'd0) test case Open

enhancement good first issue tests

chipsalliance/sv-tests#507 · 4 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Add Verilator in multiple modes Open

chipsalliance/sv-tests#548 · 7 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Some basejump_stl files are abstract base classes and should be marked parse only Open

chipsalliance/sv-tests#549 · 7 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
BlackParrot Verilog vs SystemVerilog files Open

enhancement runners tests

chipsalliance/sv-tests#580 · 3 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Contribution guide Open

documentation

chipsalliance/sv-tests#597 · 0 comments · 0 reactions · 1 assignee · Indexed Sep 14, 2026
Import the OpenSPARC as a test suite Open

import-testsuite

chipsalliance/sv-tests#619 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Add proper command line options to specify that .v files are actually .sv files Open

chipsalliance/sv-tests#662 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Blackparrot bp_top test file list as an issue Open

chipsalliance/sv-tests#701 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Publish the history of the reports somewhere Open

enhancement

chipsalliance/sv-tests#771 · 4 comments · 0 reactions · 1 assignee · Indexed Sep 14, 2026
Import XilinxUnisimLibrary as a test suite? Open

import-testsuite

chipsalliance/sv-tests#903 · 5 comments · 0 reactions · 1 assignee · Indexed Sep 14, 2026
make generate-tests fails for earlgrey out of the box Open

chipsalliance/sv-tests#913 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Auto-generate a "Language Support" page like slang's for each tool Open

chipsalliance/sv-tests#958 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Cross-check functionality in sv-tests against slang's "Language Support" page Open

chipsalliance/sv-tests#959 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Add RedPitaya to cores Open

import-testsuite

chipsalliance/sv-tests#970 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
union versus intersection testing and the testing strategy in general Open

chipsalliance/sv-tests#1214 · 2 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
IVL_UVM test suite (minimal) is now available Open

chipsalliance/sv-tests#1215 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Non-standard, but defacto standard tests Open

chipsalliance/sv-tests#1227 · 2 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
@ * is valid and should not be excluded in ivtest Open

chipsalliance/sv-tests#1315 · 14 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Pull request "Compared test results" small feature requests Open

enhancement good first issue

chipsalliance/sv-tests#1346 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Problems When Module Parameters are Passed Single Words of a Multi Bit Array in SystemVerilog but not Verilog Open

chipsalliance/sv-tests#1686 · 3 comments · 0 reactions · 2 assignees · Indexed Sep 14, 2026
[Feature] adding advanced search Open

chipsalliance/sv-tests#1700 · 2 comments · 0 reactions · 2 assignees · Indexed Sep 14, 2026
Add wav-lpddr-hw to sv-tests Open

chipsalliance/sv-tests#1723 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Suggest policy of reviewing failures before accepting new tests Open

chipsalliance/sv-tests#1871 · 3 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Include column sorting option in URL Open

chipsalliance/sv-tests#3140 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Create anchor for sub-tables Open

chipsalliance/sv-tests#3149 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
a way to make the Pyhon dependencies more hermetic ? Open

chipsalliance/sv-tests#3305 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Use standard naming of some binaries (yosys-uhdm, zachjs-sv2v) Open

chipsalliance/sv-tests#3550 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Adding svase to tools Open

chipsalliance/sv-tests#5018 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Yosys SV Support Misrepresented Due to $display Open

chipsalliance/sv-tests#5082 · 7 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
UVM-related tests come with undefined package's import Open

chipsalliance/sv-tests#5798 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Adding opl3_fpga to cores Open

chipsalliance/sv-tests#5804 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Add "vast" library to comparison Open

chipsalliance/sv-tests#6511 · 2 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Completness status Open

chipsalliance/sv-tests#8576 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
[SV3 ┬º3.3 / LRM 5.7.1] Add semantic and negative integer-literal coverage Open

chipsalliance/sv-tests#8917 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Race in tests/chapter-9/9.4.2--event_control_sim_minimal.sv Open

chipsalliance/sv-tests#9024 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026

chipsalliance/sv-tests

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