Add RedPitaya to cores

RedPitaya is a data gathering device using an FPGA. The code is open source and is built with ~30kloc SystemVerilog.
So this could make a good example of a real-world code like other cores.
They have different versions covered in their RTL, but should not be too hard to extract the files to build a final version.

Code doesn't seem to change much these days, so this could make it a stable test case:
https://github.com/RedPitaya/RedPitaya/tree/master/fpga

Start with the RedPitaya FPGA source tree linked in the issue and compare how existing cores are organized in sv-tests. Determine which RTL files and version can form a stable test case, then check the repository's core discovery and test entry points. Done means the selected RedPitaya sources are integrated and exercised by the test suite.

Written by the indexing model from the issue text.