chipsalliance / chipsalliance/chisel
Allow subword assignment
- Dominant language
- Scala
- Stars
- 4.8k
- Forks
- 658
- Avg merge
- 18h 59m
- Merged PRs (30d)
- 14
Description
class TestModule extends Module {
val io = IO(new Bundle {
val in = Input(UInt(10.W))
val bit = Input(Bool())
val out = Output(UInt(10.W))
})
io.out(0) := io.bit
}
Please make this code valid again, using bundles and vector are to slow to write, when I want to such a simple thing.
Contributor guide
Research direction
The issue provides a Scala/Chisel reproducer for assigning io.bit to io.out(0), but names no source file or test. Start by tracing how this subword assignment is handled, then find the existing assignment tests and add coverage for the shown example. Done means the example elaborates successfully without requiring a Bundle or Vec workaround.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- scala
- Domain
- compilers
- Issue type
- Feature
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 38/100