chipsalliance / chipsalliance/chisel
Need a way to turn on debug flag for treadle and verilator backend
- Dominant language
- Scala
- Stars
- 4.8k
- Forks
- 658
- Avg merge
- 18h 59m
- Merged PRs (30d)
- 14
Description
**Type of issue**: feature request
**Impact**: API addition (no impact on existing code)
**Development Phase**: request
**Other information**
See gitter conversation on 5/20/2020 @ 15:04. Chick recommended that I file this feature request issue.
**If the current behavior is a bug, please provide the steps to reproduce the problem:**
**What is the current behavior?**
I don't have a way to easily turn on debug mode for treadle and verilator backend
**What is the expected behavior?**
Be able to pass a flag from `sbt` so failing tests written in chiseltest framework can dump out more verbose output.
**Please tell us about your environment:**
libraryDependencies += "edu.berkeley.cs" %% "chiseltest" % "0.2-SNAPSHOT"
**What is the use case for changing the behavior?**
I have tests that are failing and I don't have a good way to debug it using chiseltest framework.
Contributor guide
Research direction
Start by tracing how sbt options reach the chiseltest framework and how the treadle and verilator backends are invoked. The change is complete when a flag passed from sbt enables verbose debug output for failing chiseltest tests on both backends.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- scala
- Domain
- backend, testing-qa
- Issue type
- Feature
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 35/100