Using "Flipped" on singleton Bundle results in unexpected behavior

**Type of issue**: bug report

**Impact**: unknown

**Development Phase**: request

**If the current behavior is a bug, please provide the steps to reproduce the problem:**

```scala
import chisel3._
import chisel3.stage.ChiselStage

object CicaBundle extends Bundle {
val cica = Output(Bool())
}

class Foo extends Module {
val io = IO(new Bundle {
val in = Flipped(CicaBundle)
val out = Output(Bool())
})

// io.in.cica should be an Input, but it is an Output
io.in.cica := true.B

io.out := ~io.in.cica
}

println((new ChiselStage).emitVerilog(new Foo))
```

**What is the current behavior?**

Chisel emits verilog, but `io.in.cica` is not flipped.

```verilog
module Foo(
input clock,
input reset,
output io_in_cica,
output io_out
);
assign io_in_cica = 1'h1; // @[main.scala 17:14]
assign io_out = ~io_in_cica; // @[main.scala 19:10]
endmodule
```

**What is the expected behavior?**

Since a singleton Bundle cannot be flipped, this should fail with a helpful message before outputting any FIRRTL or Verilog code.

**Please tell us about your environment:**

Version: `3.3.0`

**What is the use case for changing the behavior?**

As a beginner, I found this behavior very confusing.