Counter-intuitive user experience (UX) for simple constant addition

**Type of issue**: bug report / other enhancement

**Impact**: unknown

**Development Phase**: request

**Other information**:

Food for thought.

Consider the following simple Chisel expression (which is actually present in the bootcamp): `4.U + 4.U`. Surprisingly, it evaluates to `0` not `8`, since `4.U` is assigned a width of `3` by Chisel (i.e. `4.U` is identical to `4.U(3.W)`), and the default `+` operator is width-truncating.

We actually need to use the expression `4.U +& 4.U` to express `8.U`, which can be a bit counter-intuitive. It would be good if `4.U + 4.U` could mean `4.U(inf.W) + 4.U(inf.W) --> 8.U(inf.W)` rather than `4.U(3.W) + 4.U(3.W)`, for which the `+` operator is doing a spectacular job.

(Do width-less UInts actually exist?)

```scala
class MyOperators extends Module {
val io = IO(new Bundle {
val in = Input(UInt(4.W))
val wtf = Output(UInt())
val why = Output(UInt())
val bbq = Output(UInt())
})
// tail(add(UInt<3>("h04"), UInt<3>("h04")), 1) == 0
io.wtf := 4.U + 4.U
// add(UInt<3>("h04"), UInt<3>("h04")) == 8
io.why := 4.U +& 4.U
io.bbq := 4.U(4.W) + 4.U(4.W)
}
```
Generated circuits for reference below:
```
circuit MyOperators :
module MyOperators :
input clock : Clock
input reset : UInt<1>
output io : {flip in : UInt<4>, wtf : UInt, why : UInt, bbq : UInt}

node _T = add(UInt<3>("h04"), UInt<3>("h04")) @[cmd23.sc 8:17]
node _T_1 = tail(_T, 1) @[cmd23.sc 8:17]
io.wtf <= _T_1 @[cmd23.sc 8:10]
node _T_2 = add(UInt<3>("h04"), UInt<3>("h04")) @[cmd23.sc 9:17]
io.why <= _T_2 @[cmd23.sc 9:10]
node _T_3 = add(UInt<4>("h04"), UInt<4>("h04")) @[cmd23.sc 10:22]
node _T_4 = tail(_T_3, 1) @[cmd23.sc 10:22]
io.bbq <= _T_4 @[cmd23.sc 10:10]
```
```verilog
module MyOperators(
input clock,
input reset,
input [3:0] io_in,
output [2:0] io_wtf,
output [3:0] io_why,
output [3:0] io_bbq
);
assign io_wtf = 3'h0; // @[cmd23.sc 8:10]
assign io_why = 4'h8; // @[cmd23.sc 9:10]
assign io_bbq = 4'h8; // @[cmd23.sc 10:10]
endmodule
```