chipsalliance / chipsalliance/chisel

Add stacked source locators

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Dominant language
Scala
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Description

**Type of issue**: feature request

**Impact**: unknown

**Development Phase**: request

**Other information**
When looking at generated verilog, we see the leaf level source file such as Mux.scala. We instead need to see a stack trace of sources for this feature to be more helpful.

**Please tell us about your environment:**
Ubuntu

**What is the use case for changing the behavior?**
Faster manual debug

Contributor guide

Open the contributing guide

Assessment

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