Chisel and Treadle need an elegant Plusargs mechanism

**Type of issue**: feature request

**Impact**: no functional change | API addition (no impact on existing code) | API modification | unknown

**Development Phase**: proposal

**Other information**

**If the current behavior is a bug, please provide the steps to reproduce the problem:**

**What is the current behavior?**
There is no an elegant Plusargs mechanism

**What is the expected behavior?**
Rocket-chip use Verilog blackbox plusarg_reader to implement this. While a pure chisel/treadle solution is more elegant, so that Treadle can simulate Rocket-chip firrtl.

**Please tell us about your environment:**

**What is the use case for changing the behavior?**

No files or tests are named. Start by reviewing Rocket-chip’s Verilog blackbox plusarg_reader and how Treadle handles FIRRTL simulation; done means defining an elegant pure Chisel/Treadle plusargs mechanism that lets Treadle simulate Rocket-chip FIRRTL.

Written by the indexing model from the issue text.