Does chisel plan to support full-featured SVA?

**Type of issue**: feature request

**Impact**: API addition

**Development Phase**: request

**Other information**

We are trying to use Chisel for the CPU core design, the advanced circuit generation and design reuse features of Chisel are very suitable for digital circuit design. But Chisel is not friendly for digital circuit verification, especially for deisgn embedded SVA statement. We have to add the SVA manually after verilog generation, and do it again if modified and recompile the Chisel code.

So, does the Chisel community have plans to support full-featured SVA, including property decls and sequence exprs? Or we need to find other ways to overcome this problem.

The issue names no files, tests, or entry points. Start by tracing how Chisel is compiled to generated Verilog and clarify the intended support for SVA property declarations and sequence expressions; done would require a decided scope and corresponding implementation plan.

Written by the indexing model from the issue text.