chipsalliance / chipsalliance/chisel

Bad Error when calling .asUInt on empty Bundle

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bug
Dominant language
Scala
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Description

**Type of issue**: bug report

**Impact**: API addition (no impact on existing code)

**Development Phase**: request

**Other information**

**If the current behavior is a bug, please provide the steps to reproduce the problem:**

**What is the current behavior?**

```scala
import chisel3._
import chisel3.stage.ChiselStage

class EmptyBundle extends Bundle

class Example extends MultiIOModule {
val in = IO(Input(new EmptyBundle))
val out = IO(Output(UInt()))
out := in.asUInt
}

println(ChiselStage.emitVerilog(new Example))
```
Gives
```
Caused by: java.lang.UnsupportedOperationException: empty.tail
at scala.collection.immutable.Vector.tail(Vector.scala:201)
at scala.collection.immutable.Vector.tail(Vector.scala:69)
at chisel3.SeqUtils$.do_asUInt(SeqUtils.scala:23)
at chisel3.Aggregate.do_asUInt(Aggregate.scala:86)
at Playground$Example$$anonfun$3.apply(main.scala:11)
```

Scastie link: https://scastie.scala-lang.org/BnB4BDAySh6mIQvTgNgDiQ

**What is the expected behavior?**

Ideally it would be a proper zero-width wire, but at the very least should give a precise error message instead of `empty.tail`. I think it should remain an error until we have zero-width wires, otherwise we'll be stuck with it being single bit forever.

**Please tell us about your environment:**

**What is the use case for changing the behavior?**

Contributor guide

Open the contributing guide

Research direction

Start with the failing call in SeqUtils.scala:23 and the Aggregate.do_asUInt path identified in the stack trace. Reproduce the EmptyBundle example with ChiselStage.emitVerilog, then verify that the failure remains an error but reports a precise message rather than empty.tail.

Written by the indexing model from the issue text.

Assessment

Tech stack
scala
Domain
compilers
Issue type
Bug
Difficulty
2/5
Estimated time
1-3 hours
Activity status
Stale
Clarity
Mostly clear
Newbie friendliness
35/100

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