chipsalliance / chipsalliance/chisel
Mixing ChiselStage with ChirrtlEmitter does not work in 3.4.0-RC2
- Dominant language
- Scala
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Description
**Type of issue**: bug report
**Impact**: no functional change
**Development Phase**: request
**Other information**
**If the current behavior is a bug, please provide the steps to reproduce the problem:**
**What is the current behavior?**
Scastie link: https://scastie.scala-lang.org/BhBOK32BQRmzZLMH71tAfw
Given:
```scala
class MyModule extends Module {
val io = IO(new Bundle {
val in = Input(UInt(8.W))
val out = Output(UInt(8.W))
})
io.out := io.in
}
object MyMain extends App {
val annos = List(
ChiselGeneratorAnnotation(() => new MyModule),
TargetDirAnnotation("dir"),
RunFirrtlTransformAnnotation(new ChirrtlEmitter)
)
(new chisel3.stage.ChiselStage).execute(args, annos)
}
```
Crashes with:
```
firrtl.options.PhaseException: Multiple CustomFileEmission annotations would be serialized to the same file, '/tmp/scastie2658337669388794900/dir/MyModule.fir'
- first writer:
class: firrtl.EmittedFirrtlCircuitAnnotation
trimmed serialization: EmittedFirrtlCircuitAnnotation(EmittedFirrtlCircuit(MyModule,circuit MyModule :
- second writer:
class: chisel3.stage.ChiselCircuitAnnotation
trimmed serialization: ChiselCircuitAnnotation(Circuit(MyModule,ArrayBuffer(DefModule(MyModule@35ec0a6b
at firrtl.options.phases.WriteOutputAnnotations.$anonfun$transform$1(WriteOutputAnnotations.scala:54)
```
The fundamental issue is that both Chisel and ChirrtlEmitter want to write the same `.fir` file. In the past, we just wrote it multiple times and never noticed. The new `CustomFileEmission` API is stricter about this sort of thing so now it's an error.
**What is the expected behavior?**
It should either report a clean and precise user error, or better yet it should handle this gracefully.
**What is the use case for changing the behavior?**
Better user experience.
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Assessment
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