Lazy val ports material ports in parent of modules where the lazy val is defined

**Type of issue**: bug(?) report

**Impact**: API modification (but bugfix?)

**Development Phase**: request

**Other information**

**If the current behavior is a bug, please provide the steps to reproduce the problem:**

See my Scastie example: https://scastie.scala-lang.org/fiOI89iyRkagqH66r7OHBA
Pasted below:
```scala
import chisel3._

class ChildModule extends MultiIOModule {
val in = IO(Input(UInt(8.W)))
lazy val x = IO(Input(UInt(4.W)))
val out = IO(Output(UInt(8.W)))
out := in
}

class MyModule extends MultiIOModule {
val in = IO(Input(UInt(8.W)))
val out = IO(Output(UInt(8.W)))
val mod = Module(new ChildModule)
mod.in := in
out := mod.out
}

println(chisel3.Driver.emitVerilog(new MyModule))
```

**What is the current behavior?**

This add `x` as a port to `MyModule`, **not** to `ChildModule` as one would expect.

**What is the expected behavior?**

I'm not 100% sure what the behavior should be, maybe add `x` as a port to `ChildModule`, maybe an error.

**Please tell us about your environment:**

**What is the use case for changing the behavior?**

The main issue with this is that the behavior can differ based on whether or not you access the `lazy val`. If it is accessed, it'll materialize in `ChildModule`, if not, it materializes in `MyModule` which means if you try to drive it, you get an exception because you're driving `MyModule`s input instead of `ChildModule`s input. Basically, this is very bizarre.