Support `$` in port names

In particular, this would be useful for Blackboxing code that uses `$` in the name

Example:
https://scastie.scala-lang.org/YhPfU73XQRWaBhJvVW9ydA
```scala
import chisel3._

class MyBlackBox extends BlackBox {
val io = IO(new Bundle {
val `in$` = Input(Bool())
val `out$` = Output(Bool())
})
}

class Foo extends Module {
val io = IO(new Bundle {
val in = Input(Bool())
val out = Output(Bool())
})

val inst = Module(new MyBlackBox)
io.out := inst.io.`out$`
inst.io.`in$` := io.in
}

println((new chisel3.stage.ChiselStage).emitVerilog(new Foo))
```

Currently, we strip "illegal" characters from names for naming, but `$` is legal in Verilog

**Type of issue**: feature request

**Impact**: API addition (no impact on existing code) | API modification (?)

**Development Phase**: request | proposal

**Other information**

**If the current behavior is a bug, please provide the steps to reproduce the problem:**

**What is the current behavior?**

**What is the expected behavior?**

**Please tell us about your environment:**

**What is the use case for changing the behavior?**