chipsalliance / chipsalliance/chisel
chisel3.Driver.execute seems to emit anno file after FIRRTL invocation now
- Dominant language
- Scala
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Description
**Type of issue**: bug report
**Impact**: unknown
**Development Phase**: request
**Other information**
**If the current behavior is a bug, please provide the steps to reproduce the problem:**
GIven some small example:
```scala
import chisel3._
class ExampleModule extends Module {
val io = IO(new Bundle {
val in = Input(UInt(8.W))
val out = Output(UInt(8.W))
})
io.out := io.in
}
object ExampleTop extends App {
chisel3.Driver.execute(args, () => new ExampleModule)
}
```
Using chisel `3.2.0`
**What is the current behavior?**
`ExampleModule.anno.json` contains:
```json
[
{
"class":"firrtl.stage.FirrtlCircuitAnnotation",
"circuit":{
...
}
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~ExampleModule|ExampleModule>io_out",
"sources":[
"~ExampleModule|ExampleModule>io_in"
]
},
...
]
```
The fact that it has the `CombinationalPath` annotation suggests to me this is after running FIRRTL. It also probably shouldn't have the full circuit, seems related to https://github.com/freechipsproject/firrtl/pull/880
**What is the expected behavior?**
The annotations used to be serialized _between_ chisel and firrtl. I also would argue we shouldn't have the serialized circuit in there.
**What is the use case for changing the behavior?**
Restore older behavior
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Assessment
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