chipsalliance / chipsalliance/chisel
Current Implementation of Counter makes it impossible to create a 32bit or larger counter
- Dominant language
- Scala
- Stars
- 4.8k
- Forks
- 658
- Avg merge
- 18h 59m
- Merged PRs (30d)
- 14
Description
**Type of issue**: feature request
**Impact**: API modification
**Development Phase**: proposal
**Other information**
I submitted a PR #1363
**If the current behavior is a bug, please provide the steps to reproduce the problem:**
val x = Module(new Counter(4294967296L))
val x = Module(new Counter(4294967296))
these doesn't work
**What is the current behavior?**
Counter does not work with integers other than Int
**What is the expected behavior?**
Counter should work with long etc
**Please tell us about your environment:**
**What is the use case for changing the behavior?**
enabling all Counters to be able to handle large ints and longs without breaking backward compatibility
Contributor guide
Research direction
Start with the Counter API entry point and review PR #1363, which the issue identifies as the proposed implementation. Check how counters currently accept Int values, then verify support for larger integer and long values without breaking existing usage.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- scala
- Domain
- embedded-iot
- Issue type
- Feature
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 25/100