Bundle asUInt ignores structural width

It appears bundle packing behavior ignores the structural (defined in the Bundle def) width, at least for bundle literals. When defining a bundle literal, the .asUInt returns a different value depending on if the literal components have an explicitly specified width or not. See example below.

Potentially related to FIRRTL (I think?) not having a concept of a bundle type?

**Type of issue**: bug report

**Impact**: unknown

**Development Phase**: request

**Other information**

Discovered during implementation of #1280

**If the current behavior is a bug, please provide the steps to reproduce the problem:**

This example reproduces the behavior: https://scastie.scala-lang.org/MYZTNgqTQdOrJuUDiuV1vw
```scala
import chisel3._
import chisel3.experimental.BundleLiterals._
import chiseltest._

class LongBundle extends Bundle {
val a = UInt(32.W)
val b = UInt(32.W)
}

class Foo extends MultiIOModule {
val bun1 = (new LongBundle).Lit(_.a -> 0xBE.U, _.b -> 0xEF.U)
val bun2 = (new LongBundle).Lit(_.a -> 0xBE.U(32.W), _.b -> 0xEF.U(32.W))
chisel3.printf("bun1=%x, bun2=%x\n", bun1.asUInt(), bun2.asUInt())
}

RawTester.test(new Foo) { c =>
c.clock.step(1)
}
```

**What is the current behavior?**

The value of bun1 is different from bun2, as shown by the print:
```
bun1=0beef, bun2=0000000be000000ef
bun1=0beef, bun2=0000000be000000ef
```

**What is the expected behavior?**
Both should be equal, namely bun1 should be be000000ef (optionally with leading zeros)

**Please tell us about your environment:**

Scastie, but reproduces on Windows.

**What is the use case for changing the behavior?**