chipsalliance / chipsalliance/chisel
How about providing `pwhen` or parallelWhen
- Dominant language
- Scala
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- Merged PRs (30d)
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Description
https://github.com/freechipsproject/chisel3/blob/dbb024a9adee6d82f37e357cf8b55456674ff65c/core/src/main/scala/chisel3/When.scala#L12
There is an popular design pattern in Chisel like this:
`data := initial_data`
`when(condA) { data := dataA }`
`when(condB) { data := dataB }`
`when(condC) { data := dataC }`
and the statements can be mixed in from anywhere. in most cases in this design pattern, the when condition are parallel, that is, the order of mixing-in doesn't matter. While the current `when` semantic is a serial implementation resulting a priority Mux chain, which will introduce redundent logics.
How about providing `pwhen` or parallelWhen, where the conditions in `pwhen` are parallel and the implementation will be Mux1H. A `pwhen` has no `otherwise` or `elsewhen` statements.
`data := initial_data`
`pwhen(condA) { data := dataA }`
`pwhen(condB) { data := dataB }`
`pwhen(condC) { data := dataC }`
Contributor guide
Research direction
Start with core/src/main/scala/chisel3/When.scala at the referenced line and trace how current when, elsewhen, and otherwise semantics are implemented. Determine how a pwhen or parallelWhen API would represent independent conditions and Mux1H behavior, with no otherwise or elsewhen support; done means the proposed semantics are implemented and verified by appropriate tests.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- scala
- Domain
- compilers
- Issue type
- Feature
- Difficulty
- 5/5
- Estimated time
- Over a week
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 30/100