intel/rohd

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The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.

Stars: 489
Forks: 88
Open beginner issues: 0
Indexed issues: 122
Avg merge: 3d 23h
Merged PRs (30d): 10

Dominant language: Dart
License: BSD-3-Clause
Last GitHub push: Sep 14, 2026
Latest indexed: Sep 17, 2026
Contributing guide: Contributing guide
Code of conduct: Code of conduct
Beginner labels: help wanted good first issue

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122 open issues indexed

Add `unique` and `priority` to `If` statements Open

enhancement

intel/rohd#10 · 1 comment · 0 reactions · 1 assignee · Indexed Sep 17, 2026
Make it so that `Synthesizer`s generate an output themselves based on a `Module` Open

enhancement

intel/rohd#14 · 0 comments · 0 reactions · 1 assignee · Indexed Sep 17, 2026
Add a `NonSynthesizable` mixin Open

enhancement

intel/rohd#20 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 17, 2026
Add documentation discussing hierarchical interfaces Open

documentation enhancement

intel/rohd#47 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 17, 2026
Zero width signals get created as 1 bit signals in generated SystemVerilog Open

bug help wanted

intel/rohd#57 · 1 comment · 0 reactions · 1 assignee · Indexed Sep 17, 2026
Assertions Open

enhancement good first issue

intel/rohd#66 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 17, 2026
More complete support for signed operations Open

enhancement help wanted

intel/rohd#77 · 3 comments · 2 reactions · 0 assignees · Indexed Sep 17, 2026
Modify `Logic.changed` to trigger on `postTick` only after `glitch` Open

enhancement good first issue

intel/rohd#95 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 17, 2026
Make `Logic`'s `toString()` method more insightful Open

enhancement good first issue

intel/rohd#96 · 4 comments · 0 reactions · 1 assignee · Indexed Sep 17, 2026
Allow `Logic` signals to be re-connected Open

enhancement

intel/rohd#97 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 17, 2026
Prevent new signal connections after build/simulation has begun Open

enhancement

intel/rohd#98 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 17, 2026
Create a utility that can convert SystemVerilog modules into ROHD Open

enhancement help wanted

intel/rohd#100 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 17, 2026
`Case` and `CaseZ` matching on invalid and non-constant values Open

bug help wanted

intel/rohd#102 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 17, 2026
More testing around X/Z optimism/pessimism Open

enhancement

intel/rohd#103 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 17, 2026
Replace generic `Exception`s with more specific or ROHD-related exceptions Open

enhancement help wanted

intel/rohd#105 · 2 comments · 0 reactions · 0 assignees · Indexed Sep 17, 2026
Enable math operations on different width inputs Open

enhancement

intel/rohd#108 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 17, 2026
Collapse equivalent in-line assignments in the SystemVerilog synthesizer Open

enhancement help wanted

intel/rohd#109 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 17, 2026
Add extensive testing for zero-width `Logic`s and `LogicValue`s Open

enhancement help wanted

intel/rohd#111 · 7 comments · 0 reactions · 0 assignees · Indexed Sep 17, 2026
Add support to pipeline entire interfaces using an abstraction Open

enhancement help wanted

intel/rohd#118 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 17, 2026
Add support to "name" `Pipeline` stages and reference them by name Open

enhancement help wanted

intel/rohd#119 · 2 comments · 0 reactions · 1 assignee · Indexed Sep 17, 2026
Make `LogicValue` `toInt`, `toBigInt`, etc. return `null` when signal is invalid instead of an Exception Open

enhancement good first issue

intel/rohd#128 · 3 comments · 0 reactions · 0 assignees · Indexed Sep 17, 2026
Provide an easy method for adding comments to generated outputs Open

enhancement

intel/rohd#132 · 2 comments · 0 reactions · 0 assignees · Indexed Sep 17, 2026
Export some utilities in ROHD for others to use Open

enhancement

intel/rohd#134 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 17, 2026
Add named constants or enums Open

enhancement help wanted

intel/rohd#139 · 0 comments · 1 reaction · 0 assignees · Indexed Sep 17, 2026
Mechanism to warn about integer truncation in constants Open

enhancement help wanted

intel/rohd#142 · 4 comments · 1 reaction · 0 assignees · Indexed Sep 17, 2026
A way to group blocks of generated output Open

enhancement

intel/rohd#145 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 17, 2026
Support tagging of generated SystemVerilog `begin` and `end` Open

enhancement good first issue

intel/rohd#146 · 3 comments · 0 reactions · 1 assignee · Indexed Sep 17, 2026
Add a switch to disable synthesizer collapsing functions Open

enhancement

intel/rohd#147 · 1 comment · 1 reaction · 0 assignees · Indexed Sep 17, 2026
A double "tick" is required to generate waveform Open

bug

intel/rohd#161 · 2 comments · 0 reactions · 0 assignees · Indexed Sep 17, 2026
Time stamps are not created when the input signal is unchanged Open

bug

intel/rohd#162 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 17, 2026
Dump waves to something better than VCD Open

enhancement

intel/rohd#167 · 1 comment · 0 reactions · 1 assignee · Indexed Sep 17, 2026
`Sequential` outputs as clock inputs to other `Sequential`s trigger late in the simulator Open

bug

intel/rohd#191 · 1 comment · 0 reactions · 1 assignee · Indexed Sep 17, 2026
Long combinational chains of logic can reach stack size limit during simulation Open

bug

intel/rohd#194 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 17, 2026
Add optional logging for X generation Open

enhancement help wanted

intel/rohd#230 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 17, 2026
Add helper function(s) to "split" `Logic`s and `LogicValue`s Open

enhancement help wanted

intel/rohd#236 · 2 comments · 0 reactions · 0 assignees · Indexed Sep 17, 2026
A helper function to save generated System Verilog string as a file Open

enhancement

intel/rohd#239 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 17, 2026
Allow graceful error handling in `Simulator.throwException` Open

enhancement help wanted

intel/rohd#253 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 17, 2026
Rewrite comments on `example/tree.dart` Open

documentation enhancement

intel/rohd#268 · 3 comments · 1 reaction · 0 assignees · Indexed Sep 17, 2026
Add automation for code coverage in PRs and pushes Open

enhancement help wanted

intel/rohd#270 · 10 comments · 1 reaction · 1 assignee · Indexed Sep 17, 2026
Feature to store `WaveDumper` output in memory Open

enhancement

intel/rohd#273 · 1 comment · 1 reaction · 0 assignees · Indexed Sep 17, 2026
Add a way to add a sub-module without connecting it to any ports of the containing module Open

enhancement

intel/rohd#275 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 17, 2026
It's possible for two modules to be submodules of each other Open

bug

intel/rohd#292 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 17, 2026
Specifying the Sequential vs. Combinational driving of logic in `FiniteStateMachine` Open

documentation enhancement help wanted

intel/rohd#313 · 5 comments · 2 reactions · 0 assignees · Indexed Sep 17, 2026
Support generation of latches Open

enhancement help wanted

intel/rohd#317 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 17, 2026
The order in which `clock` is connected to module inputs affects how the circuit behaves Open

bug

intel/rohd#318 · 1 comment · 1 reaction · 0 assignees · Indexed Sep 17, 2026
Improving the `StateMachine` view in `vcd` Open

enhancement

intel/rohd#322 · 1 comment · 2 reactions · 0 assignees · Indexed Sep 17, 2026
Add the ability to configure WaveDumper to ignore internal signals Open

enhancement good first issue

intel/rohd#323 · 2 comments · 1 reaction · 0 assignees · Indexed Sep 17, 2026
Upgrade ReadyValidPipeline to support additional stalls Open

enhancement help wanted

intel/rohd#343 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 17, 2026
Support a partial assignment `Conditional` Open

enhancement help wanted

intel/rohd#378 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 17, 2026
Make "expected" message in SV testbench from SimCompare include width for invalid signals Open

enhancement

intel/rohd#396 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 17, 2026

intel/rohd

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