The order in which `clock` is connected to module inputs affects how the circuit behaves

### Describe the bug

The order in which `clock` is connected to module inputs affects how the circuit behaves.

The first screenshot shows the correct behavior, the second shows the wrong one:

* `register3` and `register4` contain unknown values for some reason
* `register0` must copy the value from `register4`, and while `register4` contains an unknown value, `register0` contains the correct value
* `register0` sets the required value in the same clock as the module receives input (as if the logic is combinational, not sequential)

**SCREENSHOT 1**


**SCREENSHOT 2**


The example itself is quite large, so perhaps others should be considered as “minimal examples” (the order of joins there affected the values of `x`/`z`):

* https://github.com/intel/rohd/issues/235#issuecomment-1468243366
* https://github.com/intel/rohd/issues/235#issuecomment-1468726233
* https://github.com/intel/rohd/issues/235#issuecomment-1469601642

### To Reproduce

1. Download code: [bug_example.zip](https://github.com/intel/rohd/files/10991736/bug_example.zip)
2. Run `example.dart`, open `waves.vcd`, check `RegisterFileControllerUnit` module signals - this is expected behavior
3. Open `bsm1d.dart`, go to line 67 `rfcu.clock <= intf.clock;` and swap it with line 68.
4. Run `example.dart`, open `waves.vcd`, check `RegisterFileControllerUnit` module signals - this is erroneous behavior

### Expected behavior

The connection order does not affect the behavior of the circuit.

### Actual behavior

The connection order affects the behavior of the circuit.

### Additional: Dart SDK info

Dart SDK version: 2.19.3 (stable) (Tue Feb 28 15:52:19 2023 +0000) on "linux_x64"

### Additional: pubspec.yaml

_No response_

### Additional: Context

ROHD v0.4.2