`Case` and `CaseZ` matching on invalid and non-constant values

## Describe the bug
The `CaseZ` matching logic checks for `LogicValue` equality, which includes comparing `z` and `x` invalid values. If a non-constant floating signal is used as an input in a `CaseItem`, then the `z` could match as a wildcard.

Does this match SystemVerilog behavior? Even if it does, this seems dangerous for simulation vs. synthesis. Undefined behavior should drive X.

Additionally, when there's an X on the case item (either constant or non-constant), that should be driving X out of the Case items rather than just failing to match.

If an expression in a `CaseZ` item has a floating value, the whole output gets driven as X currently. There needs to be wildcard matching on constant expressions for `CaseZ`.

## To Reproduce
Create a `CaseZ` statement where a `CaseItem` has a floating non-constant signal as an input.

## Expected behavior
Ideally, the outputs should probably drive `x` since this is undefined behavior. The implementation is tricky, because there would need to be some check whether a signal is a constant value or may dynamically change.

## Actual behavior
A floating input in a `CaseItem` could match as a wild card.