Make it so that `Synthesizer`s generate an output themselves based on a `Module`

Right now, `Module` has a method `generateSynth` which uses a `SynthBuilder` and `SystemVerilogSynthesizer` to generate SystemVerilog file contents. It would be better if `Synthesizer` had a function that consumes `Module`s directly and returns/generates the file contents. A new `Synthesizer` should not require a new method in `Module`.