Zero width signals get created as 1 bit signals in generated SystemVerilog
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bug
help wanted
- Dominant language
- Dart
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Description
## Describe the bug
Zero width signals get created as 1 bit signals in generated SystemVerilog
## To Reproduce
Make a zero-bit port for a module and generate the SystemVerilog
## Expected behavior
No signal added
## Actual behavior
1 bit signal added
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