Add a switch to disable synthesizer collapsing functions

## Motivation
Sometimes users who are interested in the readability of generated SystemVerilog or ROHD developers are curious about how in-line modules and assignment collapsing are performed to create the final output. A flag to disable this would be useful in these situations.

## Desired solution
A flag (maybe per-module, maybe per-synthesizer) that disables collapsing like `_collapseAssignments` and `_collapseChainableModules`.