Support a partial assignment `Conditional`

### Motivation

See https://github.com/intel/rohd/discussions/363

It might be nice to assign part of a signal conditionally.

### Desired solution

A function on `Logic` which could do a partial set (maybe similar to `withSet`) of bits of a signal.

One important thing to consider are new cases that show up with this feature. For example, in a `Combinational`, if some bits are not assigned, we need to drive them to `x` to ensure we don't simulate an inferred latch. There could be other tricky things like that.

Generated verilog is controlled by the `Conditional` so this should be achievable. There may be some tricky business with legal verilog generation for arrays?

### Alternatives considered

_No response_

### Additional details

_No response_