Enable math operations on different width inputs

## Motivation
It would be nice to provide a mechanism to do math on signals/values of different widths when it is unambiguous. It's also potentially useful to have a larger output than either input.

## Desired solution
There might be some scenarios where behavior can be safely inferred with just the operator and no additional inputs. In other cases, perhaps a special operator or function is required to enable users to explicitly handle width ambiguity.

## Alternatives considered
Many operations always require exact width matching (as it is currently), meaning people should pad their values before performing the operation.

## Additional details
SystemVerilog has features like this, though some may be a little dangerous.