Assertions

## Motivation
SystemVerilog assertions are valuable for design and verification. It would be nice to have assertions in ROHD that give similar functionality, but that are also "synthesizable" to behavioral SystemVerilog so that simulations of generated code can also benefit from the assertions.

## Desired solution
An `Assertion` type that acts like an assert or Exception in Dart, but is also synthesizable to the generated output representation.

## Alternatives considered
Existing assertions and exceptions in Dart are already nice, but not synthesizable to the generated representation.