lowRISC/ibex

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Ibex is a small 32-bit RISC-V CPU core with high-level of verification (previously known as zero-riscy)

Stars: 2.1k
Forks: 810
Open beginner issues: 0
Indexed issues: 205
Avg merge: 5d 23h
Merged PRs (30d): 9

Dominant language: SystemVerilog
License: Apache-2.0
Last GitHub push: Sep 17, 2026
Latest indexed: Sep 19, 2026
Contributing guide: Contributing guide
Code of conduct: No code of conduct
Beginner labels: good first issue

Beginner friendly Everything

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205 open issues indexed

Ask a question related to Ibex Open

Type:Question

Difficulty 5/5 Over a week Newbie friendliness 15/100

lowRISC/ibex#1961 · 3 comments · Opened Dec 6, 2022
mismatch between spike sim and rtl sim Open

Type:Question

Difficulty 4/5 3-5 days Newbie friendliness 25/100

lowRISC/ibex#1959 · 2 comments · Opened Dec 1, 2022
.S file is not generated for riscv_arithmetic_basic_test Open

Type:Question

Difficulty 4/5 3-5 days Newbie friendliness 35/100

lowRISC/ibex#1956 · 2 comments · Opened Nov 25, 2022
Error when I make in ibex UVM DV Open

Component:DV Type:Bug Type:Question

Difficulty 4/5 3-5 days Newbie friendliness 20/100

lowRISC/ibex#1955 · 3 comments · Opened Nov 22, 2022
[cosim] Sort out error/pmp failure behaviour on unaligned accesses Open

Component:DV Priority:P3

Difficulty 4/5 3-5 days Newbie friendliness 35/100

lowRISC/ibex#1948 · 1 comment · Opened Nov 17, 2022
[dv] PMP Coverage Holes Open

Component:DV Priority:P2

Difficulty 4/5 3-5 days Newbie friendliness 35/100

lowRISC/ibex#1944 · 5 comments · Opened Nov 16, 2022
bitmanip s Open

Type:Question

Difficulty 4/5 3-5 days Newbie friendliness 20/100

lowRISC/ibex#1941 · Opened Nov 16, 2022
[dv] Build a regression system for directed simple system co-sim tests Open

Component:DV Component:Test Type:Enhancement

Difficulty 5/5 Over a week Newbie friendliness 25/100

lowRISC/ibex#1936 · Opened Nov 15, 2022
[dv] Psuedo instruction coverage for Bitmanip Open

Difficulty 4/5 3-5 days Newbie friendliness 35/100

lowRISC/ibex#1926 · Opened Nov 13, 2022
[dv] Small architectural coverage issues to investigate Open

Component:DV Priority:P3 Type:Task

Difficulty 4/5 3-5 days Newbie friendliness 25/100

lowRISC/ibex#1925 · 1 comment · Opened Nov 13, 2022
[dv] Add force pass and terminate functionality to UVM base test Open

Difficulty 2/5 1-3 hours Newbie friendliness 40/100

lowRISC/ibex#1892 · 1 comment · Opened Nov 2, 2022
Problem on Building Simulation with RV32E Open

Type:Question

Difficulty 3/5 1-2 days Newbie friendliness 25/100

lowRISC/ibex#1860 · 7 comments · Opened Oct 18, 2022
Record when a testcase fails by the double_fault detector, add indicator to summary logfile Open

Type:Enhancement

Difficulty 4/5 3-5 days Newbie friendliness 15/100

lowRISC/ibex#1857 · Opened Oct 14, 2022
Consider adding explicit enable for qualifying DBG_CAUSE Open

Component:RTL Type:Enhancement

Difficulty 5/5 Over a week Newbie friendliness 25/100

lowRISC/ibex#1856 · Opened Oct 14, 2022
[dv] Randomize hart_id Open

Component:DV Type:Enhancement

Difficulty 3/5 1-2 days Newbie friendliness 45/100

lowRISC/ibex#1852 · Opened Oct 14, 2022
[dv] Prettify invalid option to column Open

Type:Bug

Difficulty 2/5 1-3 hours Newbie friendliness 48/100

lowRISC/ibex#1843 · 1 comment · Opened Oct 7, 2022
Document behaviour for insns with UNSPECIFIED behaviour while in debug mode Open

Component:Doc Component:DV

Difficulty 2/5 1-3 hours Newbie friendliness 35/100

lowRISC/ibex#1840 · Opened Oct 6, 2022
[dv/uvm] Detect changes in Makefile arguments Open

Component:DV Type:Enhancement

Difficulty 4/5 3-5 days Newbie friendliness 30/100

lowRISC/ibex#1836 · Opened Oct 5, 2022
Clone task: [rv_core_ibex,dv] Integrate the Ibex "core_ibex" tests with dvsim Open

Difficulty 5/5 Over a week Newbie friendliness 15/100

lowRISC/ibex#1806 · Opened Sep 7, 2022
[rtl] Issues with memory and instruction fetch errors with branch prediction enabled Open

Component:RTL Type:Bug

Difficulty 4/5 3-5 days Newbie friendliness 42/100

lowRISC/ibex#1803 · 4 comments · Opened Sep 6, 2022
[dv] CSR Coverage Waiver Open

Component:DV Priority:P3 Waive:M2

Difficulty 4/5 3-5 days Newbie friendliness 25/100

lowRISC/ibex#1795 · 3 comments · Opened Aug 24, 2022
Further core_ibex uvm build system improvements Open

Type:Enhancement

Difficulty 4/5 3-5 days Newbie friendliness 25/100

lowRISC/ibex#1778 · Opened Aug 16, 2022
[dv] Testbench memory region checker Open

Component:DV Type:Enhancement

Difficulty 5/5 Over a week Newbie friendliness 25/100

lowRISC/ibex#1753 · 2 comments · Opened Aug 10, 2022
Ibex does not reflect instruction memory changes to ICache Open

Component:Doc Component:DV Type:Enhancement

Difficulty 5/5 Over a week Newbie friendliness 25/100

lowRISC/ibex#1738 · 2 comments · Opened Aug 1, 2022
[dv] Consider explicit PMP fail/pass checking Open

Component:DV Type:Enhancement

Difficulty 4/5 3-5 days Newbie friendliness 35/100

lowRISC/ibex#1709 · 1 comment · Opened Jul 18, 2022
Changing Memory Width of Ibex Open

Type:Question

Difficulty 5/5 Over a week Newbie friendliness 25/100

lowRISC/ibex#1707 · Opened Jul 15, 2022
[ot][docs] Check OT CI for non-Cosim related tooling instructions and remove if found. Open

Component:Doc Type:Enhancement

lowRISC/ibex#1684 · 1 comment · 2 assignees · Opened Jun 29, 2022
[dv] Generic Code Coverage Waiver Tool Open

Component:Tool-and-Build

lowRISC/ibex#1683 · 3 comments · 1 assignee · Opened Jun 23, 2022
Simulating Arty A7 35 example in Vivado causes error due to hack in ibex_if_stage.sv Open

Type:Bug

Difficulty 4/5 3-5 days Newbie friendliness 35/100

lowRISC/ibex#1679 · 3 comments · Opened Jun 10, 2022
Spike log issue Open

Type:Question

lowRISC/ibex#1669 · 7 comments · 1 assignee · Opened May 28, 2022
Unable to build simple sytstem Open

Status:FlagToClose Type:Question

Difficulty 3/5 1-2 days Newbie friendliness 25/100

lowRISC/ibex#1639 · 4 comments · Opened Apr 27, 2022
HW breakpoints: "invalid hex 116" message from GDB during Opentitan Verilator simulation Open

Type:Question

Difficulty 4/5 3-5 days Newbie friendliness 25/100

lowRISC/ibex#1638 · 3 comments · Opened Apr 26, 2022
Teach auto-generated interrupt handlers to clear interrupts again Open

Difficulty 4/5 3-5 days Newbie friendliness 35/100

lowRISC/ibex#1570 · 2 comments · Opened Mar 17, 2022
Migrate all remaining test sequences to use cosim Open

Component:Test Component:TestFW Priority:P2

lowRISC/ibex#1567 · 5 comments · 1 assignee · Opened Mar 16, 2022
Updating Ibex simple system ISA string Open

lowRISC/ibex#1548 · 2 comments · 1 assignee · Opened Mar 4, 2022
How do I disable I$ parallel memory request whenever there is a branch and it's a tag hit? Open

Status:FlagToClose Type:Question

Difficulty 5/5 Over a week Newbie friendliness 20/100

lowRISC/ibex#1528 · 8 comments · Opened Feb 11, 2022
riscv_debug_wfi_test failed Open

Type:Bug

Difficulty 3/5 1-2 days Newbie friendliness 35/100

lowRISC/ibex#1499 · 3 comments · Opened Dec 24, 2021
riscv_nested_interrupt_test case failed Open

Status:FlagToClose Type:Question

Difficulty 3/5 1-2 days Newbie friendliness 35/100

lowRISC/ibex#1496 · 3 comments · Opened Dec 21, 2021
[icache,dv] Minor tidyups after dropping PMP interface Open

Component:DV Type:Cleanup Type:Task Waive:M2

Difficulty 4/5 3-5 days Newbie friendliness 25/100

lowRISC/ibex#1489 · 5 comments · Opened Dec 10, 2021
[ci] Let's try to integrate a Yosys synthesis flow into CI Open

Component:Tool-and-Build Type:Enhancement

Difficulty 5/5 Over a week Newbie friendliness 25/100

lowRISC/ibex#1481 · 4 comments · Opened Dec 2, 2021
Questions about dummy instruction insertion (instructions from if-stage skid buffer can get lost) Open

Component:RTL Type:Bug Type:Question

lowRISC/ibex#1479 · 4 comments · 1 assignee · Opened Nov 30, 2021
Instruction for next program counter after mret executed first before instruction at mret target Open

Component:RTL Type:Bug Type:Question

Difficulty 4/5 3-5 days Newbie friendliness 25/100

lowRISC/ibex#1465 · 2 comments · Opened Oct 28, 2021
Verifying instruction memory faults with the ICache Open

Component:DV Priority:P3 Type:Enhancement

Difficulty 5/5 Over a week Newbie friendliness 20/100

lowRISC/ibex#1451 · 2 comments · Opened Oct 8, 2021
Add support for mtvec direct mode Open

Component:RTL Type:Enhancement

Difficulty 4/5 3-5 days Newbie friendliness 30/100

lowRISC/ibex#1419 · 2 comments · Opened Aug 5, 2021
Violation of the Data Independent Timing property for misaligned Load and Store Instructions Open

Component:RTL Type:Bug

Difficulty 5/5 Over a week Newbie friendliness 25/100

lowRISC/ibex#1414 · 4 comments · Opened Jul 29, 2021
[dv] riscv_pmp_out_of_bounds_test fails with sim mismatch Open

Component:DV Type:Bug

Difficulty 4/5 3-5 days Newbie friendliness 25/100

lowRISC/ibex#1375 · 1 comment · Opened Jun 3, 2021
Display configuration parameters in Verilator simulation Open

Component:Tool-and-Build Good First Issue Type:Enhancement

Difficulty 4/5 3-5 days Newbie friendliness 35/100

lowRISC/ibex#1364 · 1 comment · Opened May 26, 2021
RFC: make misa.C writeable Open

Component:RTL Type:Enhancement Type:Question

Difficulty 5/5 Over a week Newbie friendliness 25/100

lowRISC/ibex#1353 · Opened May 5, 2021
[dv] Improve riscv_csr_test Open

Component:DV Priority:P3 Type:Enhancement

Difficulty 4/5 3-5 days Newbie friendliness 45/100

lowRISC/ibex#1337 · 3 comments · Opened Apr 14, 2021
[dv] Enable multiple configurations for CSR test Open

Component:DV Priority:P3 Type:Enhancement

Difficulty 5/5 Over a week Newbie friendliness 25/100

lowRISC/ibex#1333 · 1 comment · Opened Apr 13, 2021

lowRISC/ibex

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