[dv] Testbench memory region checker
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- Dominant language
- SystemVerilog
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Description
In https://github.com/lowRISC/ibex/pull/1745#issuecomment-1209244008 @hcallahan-lowrisc highlights that certain memory acceses generated by a particular test may be incorrect in the sense that we don't intend for the test to access that area of memory, but there's some bug in the generated code we're running.
To help catch these create a configurable access checker that connect to a memory bus monitor. It should be configurable to be able to produce warnings or error when certain accesses are seen to certain regions.
Defining exact capabilities (e.g. more precise definitions of 'certain' above) forms part of this task.
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start with the linked pull request comment and the memory bus monitor integration points; the payload does not name specific files or tests. Define the supported memory-region rules and warning/error behavior, then verify that generated accesses to configured regions are reported at the selected severity.
Written by the indexing model from the issue text.
Assessment
- Domain
- testing-qa
- Issue type
- Feature
- Difficulty
- 5/5
- Estimated time
- Over a week
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 25/100